mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-26 23:54:15 +01:00
480 lines
13 KiB
Verilog
480 lines
13 KiB
Verilog
// This is free and unencumbered software released into the public domain.
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//
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// Anyone is free to copy, modify, publish, use, compile, sell, or
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// distribute this software, either in source code form or as a compiled
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// binary, for any purpose, commercial or non-commercial, and by any
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// means.
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`timescale 1 ns / 1 ps
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`ifndef VERILATOR
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module testbench #(
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parameter AXI_TEST = 0,
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parameter VERBOSE = 0
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);
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reg clk = 1;
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reg resetn = 0;
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wire trap;
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always #5 clk = ~clk;
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initial begin
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repeat (100) @(posedge clk);
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resetn <= 1;
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end
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initial begin
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if ($test$plusargs("vcd")) begin
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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end
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repeat (1000000) @(posedge clk);
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$display("TIMEOUT");
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$finish;
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end
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wire trace_valid;
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wire [35:0] trace_data;
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integer trace_file;
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initial begin
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if ($test$plusargs("trace")) begin
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trace_file = $fopen("testbench.trace", "w");
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repeat (10) @(posedge clk);
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while (!trap) begin
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@(posedge clk);
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if (trace_valid)
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$fwrite(trace_file, "%x\n", trace_data);
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end
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$fclose(trace_file);
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$display("Finished writing testbench.trace.");
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end
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end
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picorv32_wrapper #(
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.AXI_TEST (AXI_TEST),
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.VERBOSE (VERBOSE)
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) top (
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.clk(clk),
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.resetn(resetn),
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.trap(trap),
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.trace_valid(trace_valid),
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.trace_data(trace_data)
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);
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endmodule
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`endif
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module picorv32_wrapper #(
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parameter AXI_TEST = 0,
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parameter VERBOSE = 0
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) (
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input clk,
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input resetn,
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output trap,
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output trace_valid,
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output [35:0] trace_data
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);
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wire tests_passed;
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reg [31:0] irq = 0;
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reg [15:0] count_cycle = 0;
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always @(posedge clk) count_cycle <= resetn ? count_cycle + 1 : 0;
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always @* begin
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irq = 0;
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irq[4] = &count_cycle[12:0];
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irq[5] = &count_cycle[15:0];
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end
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wire mem_axi_awvalid;
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wire mem_axi_awready;
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wire [31:0] mem_axi_awaddr;
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wire [ 2:0] mem_axi_awprot;
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wire mem_axi_wvalid;
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wire mem_axi_wready;
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wire [31:0] mem_axi_wdata;
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wire [ 3:0] mem_axi_wstrb;
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wire mem_axi_bvalid;
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wire mem_axi_bready;
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wire mem_axi_arvalid;
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wire mem_axi_arready;
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wire [31:0] mem_axi_araddr;
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wire [ 2:0] mem_axi_arprot;
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wire mem_axi_rvalid;
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wire mem_axi_rready;
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wire [31:0] mem_axi_rdata;
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axi4_memory #(
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.AXI_TEST (AXI_TEST),
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.VERBOSE (VERBOSE)
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) mem (
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.clk (clk ),
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.mem_axi_awvalid (mem_axi_awvalid ),
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.mem_axi_awready (mem_axi_awready ),
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.mem_axi_awaddr (mem_axi_awaddr ),
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.mem_axi_awprot (mem_axi_awprot ),
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.mem_axi_wvalid (mem_axi_wvalid ),
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.mem_axi_wready (mem_axi_wready ),
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.mem_axi_wdata (mem_axi_wdata ),
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.mem_axi_wstrb (mem_axi_wstrb ),
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.mem_axi_bvalid (mem_axi_bvalid ),
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.mem_axi_bready (mem_axi_bready ),
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.mem_axi_arvalid (mem_axi_arvalid ),
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.mem_axi_arready (mem_axi_arready ),
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.mem_axi_araddr (mem_axi_araddr ),
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.mem_axi_arprot (mem_axi_arprot ),
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.mem_axi_rvalid (mem_axi_rvalid ),
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.mem_axi_rready (mem_axi_rready ),
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.mem_axi_rdata (mem_axi_rdata ),
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.tests_passed (tests_passed )
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);
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`ifdef RISCV_FORMAL
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wire rvfi_valid;
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wire [63:0] rvfi_order;
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wire [31:0] rvfi_insn;
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wire rvfi_trap;
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wire rvfi_halt;
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wire rvfi_intr;
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wire [4:0] rvfi_rs1_addr;
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wire [4:0] rvfi_rs2_addr;
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wire [31:0] rvfi_rs1_rdata;
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wire [31:0] rvfi_rs2_rdata;
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wire [4:0] rvfi_rd_addr;
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wire [31:0] rvfi_rd_wdata;
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wire [31:0] rvfi_pc_rdata;
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wire [31:0] rvfi_pc_wdata;
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wire [31:0] rvfi_mem_addr;
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wire [3:0] rvfi_mem_rmask;
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wire [3:0] rvfi_mem_wmask;
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wire [31:0] rvfi_mem_rdata;
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wire [31:0] rvfi_mem_wdata;
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`endif
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picorv32_axi #(
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`ifndef SYNTH_TEST
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`ifdef SP_TEST
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.ENABLE_REGS_DUALPORT(0),
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`endif
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`ifdef COMPRESSED_ISA
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.COMPRESSED_ISA(1),
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`endif
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.ENABLE_MUL(1),
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.ENABLE_DIV(1),
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.ENABLE_IRQ(1),
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.ENABLE_TRACE(1)
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`endif
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) uut (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_axi_awvalid(mem_axi_awvalid),
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.mem_axi_awready(mem_axi_awready),
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.mem_axi_awaddr (mem_axi_awaddr ),
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.mem_axi_awprot (mem_axi_awprot ),
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.mem_axi_wvalid (mem_axi_wvalid ),
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.mem_axi_wready (mem_axi_wready ),
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.mem_axi_wdata (mem_axi_wdata ),
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.mem_axi_wstrb (mem_axi_wstrb ),
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.mem_axi_bvalid (mem_axi_bvalid ),
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.mem_axi_bready (mem_axi_bready ),
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.mem_axi_arvalid(mem_axi_arvalid),
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.mem_axi_arready(mem_axi_arready),
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.mem_axi_araddr (mem_axi_araddr ),
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.mem_axi_arprot (mem_axi_arprot ),
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.mem_axi_rvalid (mem_axi_rvalid ),
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.mem_axi_rready (mem_axi_rready ),
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.mem_axi_rdata (mem_axi_rdata ),
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.irq (irq ),
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`ifdef RISCV_FORMAL
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.rvfi_valid (rvfi_valid ),
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.rvfi_order (rvfi_order ),
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.rvfi_insn (rvfi_insn ),
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.rvfi_trap (rvfi_trap ),
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.rvfi_halt (rvfi_halt ),
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.rvfi_intr (rvfi_intr ),
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.rvfi_rs1_addr (rvfi_rs1_addr ),
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.rvfi_rs2_addr (rvfi_rs2_addr ),
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.rvfi_rs1_rdata (rvfi_rs1_rdata ),
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.rvfi_rs2_rdata (rvfi_rs2_rdata ),
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.rvfi_rd_addr (rvfi_rd_addr ),
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.rvfi_rd_wdata (rvfi_rd_wdata ),
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.rvfi_pc_rdata (rvfi_pc_rdata ),
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.rvfi_pc_wdata (rvfi_pc_wdata ),
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.rvfi_mem_addr (rvfi_mem_addr ),
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.rvfi_mem_rmask (rvfi_mem_rmask ),
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.rvfi_mem_wmask (rvfi_mem_wmask ),
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.rvfi_mem_rdata (rvfi_mem_rdata ),
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.rvfi_mem_wdata (rvfi_mem_wdata ),
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`endif
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.trace_valid (trace_valid ),
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.trace_data (trace_data )
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);
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`ifdef RISCV_FORMAL
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picorv32_rvfimon rvfi_monitor (
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.clock (clk ),
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.reset (!resetn ),
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.rvfi_valid (rvfi_valid ),
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.rvfi_order (rvfi_order ),
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.rvfi_insn (rvfi_insn ),
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.rvfi_trap (rvfi_trap ),
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.rvfi_halt (rvfi_halt ),
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.rvfi_intr (rvfi_intr ),
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.rvfi_rs1_addr (rvfi_rs1_addr ),
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.rvfi_rs2_addr (rvfi_rs2_addr ),
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.rvfi_rs1_rdata (rvfi_rs1_rdata),
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.rvfi_rs2_rdata (rvfi_rs2_rdata),
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.rvfi_rd_addr (rvfi_rd_addr ),
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.rvfi_rd_wdata (rvfi_rd_wdata ),
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.rvfi_pc_rdata (rvfi_pc_rdata ),
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.rvfi_pc_wdata (rvfi_pc_wdata ),
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.rvfi_mem_addr (rvfi_mem_addr ),
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.rvfi_mem_rmask (rvfi_mem_rmask),
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.rvfi_mem_wmask (rvfi_mem_wmask),
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.rvfi_mem_rdata (rvfi_mem_rdata),
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.rvfi_mem_wdata (rvfi_mem_wdata)
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);
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`endif
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reg [1023:0] firmware_file;
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initial begin
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if (!$value$plusargs("firmware=%s", firmware_file))
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firmware_file = "firmware/firmware.hex";
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$readmemh(firmware_file, mem.memory);
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end
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integer cycle_counter;
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always @(posedge clk) begin
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cycle_counter <= resetn ? cycle_counter + 1 : 0;
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if (resetn && trap) begin
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`ifndef VERILATOR
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repeat (10) @(posedge clk);
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`endif
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$display("TRAP after %1d clock cycles", cycle_counter);
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if (tests_passed) begin
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$display("ALL TESTS PASSED.");
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$finish;
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end else begin
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$display("ERROR!");
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if ($test$plusargs("noerror"))
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$finish;
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$stop;
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end
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end
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end
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endmodule
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module axi4_memory #(
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parameter AXI_TEST = 0,
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parameter VERBOSE = 0
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) (
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/* verilator lint_off MULTIDRIVEN */
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input clk,
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input mem_axi_awvalid,
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output reg mem_axi_awready,
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input [31:0] mem_axi_awaddr,
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input [ 2:0] mem_axi_awprot,
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input mem_axi_wvalid,
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output reg mem_axi_wready,
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input [31:0] mem_axi_wdata,
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input [ 3:0] mem_axi_wstrb,
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output reg mem_axi_bvalid,
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input mem_axi_bready,
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input mem_axi_arvalid,
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output reg mem_axi_arready,
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input [31:0] mem_axi_araddr,
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input [ 2:0] mem_axi_arprot,
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output reg mem_axi_rvalid,
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input mem_axi_rready,
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output reg [31:0] mem_axi_rdata,
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output reg tests_passed
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);
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reg [31:0] memory [0:128*1024/4-1] /* verilator public */;
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reg verbose;
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initial verbose = $test$plusargs("verbose") || VERBOSE;
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reg axi_test;
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initial axi_test = $test$plusargs("axi_test") || AXI_TEST;
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initial begin
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mem_axi_awready = 0;
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mem_axi_wready = 0;
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mem_axi_bvalid = 0;
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mem_axi_arready = 0;
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mem_axi_rvalid = 0;
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tests_passed = 0;
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end
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reg [63:0] xorshift64_state = 64'd88172645463325252;
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task xorshift64_next;
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begin
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// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
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xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
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xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
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xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
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end
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endtask
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reg [2:0] fast_axi_transaction = ~0;
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reg [4:0] async_axi_transaction = ~0;
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reg [4:0] delay_axi_transaction = 0;
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always @(posedge clk) begin
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if (axi_test) begin
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xorshift64_next;
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{fast_axi_transaction, async_axi_transaction, delay_axi_transaction} <= xorshift64_state;
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end
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end
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reg latched_raddr_en = 0;
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reg latched_waddr_en = 0;
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reg latched_wdata_en = 0;
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reg fast_raddr = 0;
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reg fast_waddr = 0;
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reg fast_wdata = 0;
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reg [31:0] latched_raddr;
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reg [31:0] latched_waddr;
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reg [31:0] latched_wdata;
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reg [ 3:0] latched_wstrb;
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reg latched_rinsn;
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task handle_axi_arvalid; begin
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mem_axi_arready <= 1;
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latched_raddr = mem_axi_araddr;
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latched_rinsn = mem_axi_arprot[2];
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latched_raddr_en = 1;
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fast_raddr <= 1;
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end endtask
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task handle_axi_awvalid; begin
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mem_axi_awready <= 1;
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latched_waddr = mem_axi_awaddr;
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latched_waddr_en = 1;
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fast_waddr <= 1;
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end endtask
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task handle_axi_wvalid; begin
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mem_axi_wready <= 1;
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latched_wdata = mem_axi_wdata;
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latched_wstrb = mem_axi_wstrb;
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latched_wdata_en = 1;
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fast_wdata <= 1;
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end endtask
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task handle_axi_rvalid; begin
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if (verbose)
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$display("RD: ADDR=%08x DATA=%08x%s", latched_raddr, memory[latched_raddr >> 2], latched_rinsn ? " INSN" : "");
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if (latched_raddr < 128*1024) begin
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mem_axi_rdata <= memory[latched_raddr >> 2];
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mem_axi_rvalid <= 1;
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latched_raddr_en = 0;
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end else begin
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$display("OUT-OF-BOUNDS MEMORY READ FROM %08x", latched_raddr);
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$finish;
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end
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end endtask
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task handle_axi_bvalid; begin
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if (verbose)
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$display("WR: ADDR=%08x DATA=%08x STRB=%04b", latched_waddr, latched_wdata, latched_wstrb);
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if (latched_waddr < 128*1024) begin
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if (latched_wstrb[0]) memory[latched_waddr >> 2][ 7: 0] <= latched_wdata[ 7: 0];
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if (latched_wstrb[1]) memory[latched_waddr >> 2][15: 8] <= latched_wdata[15: 8];
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if (latched_wstrb[2]) memory[latched_waddr >> 2][23:16] <= latched_wdata[23:16];
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if (latched_wstrb[3]) memory[latched_waddr >> 2][31:24] <= latched_wdata[31:24];
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end else
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if (latched_waddr == 32'h1000_0000) begin
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if (verbose) begin
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if (32 <= latched_wdata && latched_wdata < 128)
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$display("OUT: '%c'", latched_wdata[7:0]);
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else
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$display("OUT: %3d", latched_wdata);
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end else begin
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$write("%c", latched_wdata[7:0]);
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`ifndef VERILATOR
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$fflush();
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`endif
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end
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end else
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if (latched_waddr == 32'h2000_0000) begin
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if (latched_wdata == 123456789)
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tests_passed = 1;
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end else begin
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$display("OUT-OF-BOUNDS MEMORY WRITE TO %08x", latched_waddr);
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$finish;
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end
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mem_axi_bvalid <= 1;
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latched_waddr_en = 0;
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latched_wdata_en = 0;
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end endtask
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always @(negedge clk) begin
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if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && async_axi_transaction[0]) handle_axi_arvalid;
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if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && async_axi_transaction[1]) handle_axi_awvalid;
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if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && async_axi_transaction[2]) handle_axi_wvalid;
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if (!mem_axi_rvalid && latched_raddr_en && async_axi_transaction[3]) handle_axi_rvalid;
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if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && async_axi_transaction[4]) handle_axi_bvalid;
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end
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always @(posedge clk) begin
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mem_axi_arready <= 0;
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mem_axi_awready <= 0;
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mem_axi_wready <= 0;
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fast_raddr <= 0;
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fast_waddr <= 0;
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fast_wdata <= 0;
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if (mem_axi_rvalid && mem_axi_rready) begin
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mem_axi_rvalid <= 0;
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end
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if (mem_axi_bvalid && mem_axi_bready) begin
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mem_axi_bvalid <= 0;
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end
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if (mem_axi_arvalid && mem_axi_arready && !fast_raddr) begin
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latched_raddr = mem_axi_araddr;
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latched_rinsn = mem_axi_arprot[2];
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latched_raddr_en = 1;
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end
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if (mem_axi_awvalid && mem_axi_awready && !fast_waddr) begin
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latched_waddr = mem_axi_awaddr;
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latched_waddr_en = 1;
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end
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if (mem_axi_wvalid && mem_axi_wready && !fast_wdata) begin
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latched_wdata = mem_axi_wdata;
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latched_wstrb = mem_axi_wstrb;
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latched_wdata_en = 1;
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end
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if (mem_axi_arvalid && !(latched_raddr_en || fast_raddr) && !delay_axi_transaction[0]) handle_axi_arvalid;
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if (mem_axi_awvalid && !(latched_waddr_en || fast_waddr) && !delay_axi_transaction[1]) handle_axi_awvalid;
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if (mem_axi_wvalid && !(latched_wdata_en || fast_wdata) && !delay_axi_transaction[2]) handle_axi_wvalid;
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if (!mem_axi_rvalid && latched_raddr_en && !delay_axi_transaction[3]) handle_axi_rvalid;
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if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && !delay_axi_transaction[4]) handle_axi_bvalid;
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end
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endmodule
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