mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-30 01:04:13 +01:00
586 lines
16 KiB
C
586 lines
16 KiB
C
// See LICENSE for license details.
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#ifndef __TEST_MACROS_SCALAR_H
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#define __TEST_MACROS_SCALAR_H
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#-----------------------------------------------------------------------
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# Helper macros
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#-----------------------------------------------------------------------
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#define TEST_CASE( testnum, testreg, correctval, code... ) \
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test_ ## testnum: \
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code; \
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li x29, correctval; \
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li TESTNUM, testnum; \
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bne testreg, x29, fail;
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# We use a macro hack to simpify code generation for various numbers
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# of bubble cycles.
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#define TEST_INSERT_NOPS_0
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#define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0
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#define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1
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#define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2
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#define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3
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#define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4
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#define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5
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#define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6
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#define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7
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#define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8
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#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
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#-----------------------------------------------------------------------
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# RV64UI MACROS
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#-----------------------------------------------------------------------
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#-----------------------------------------------------------------------
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# Tests for instructions with immediate operand
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#-----------------------------------------------------------------------
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#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
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#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
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TEST_CASE( testnum, x3, result, \
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li x1, val1; \
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inst x3, x1, SEXT_IMM(imm); \
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)
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#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
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TEST_CASE( testnum, x1, result, \
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li x1, val1; \
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inst x1, x1, SEXT_IMM(imm); \
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)
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#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
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TEST_CASE( testnum, x6, result, \
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li x4, 0; \
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1: li x1, val1; \
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inst x3, x1, SEXT_IMM(imm); \
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TEST_INSERT_NOPS_ ## nop_cycles \
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addi x6, x3, 0; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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)
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#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
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TEST_CASE( testnum, x3, result, \
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li x4, 0; \
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1: li x1, val1; \
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TEST_INSERT_NOPS_ ## nop_cycles \
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inst x3, x1, SEXT_IMM(imm); \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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)
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#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
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TEST_CASE( testnum, x1, result, \
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inst x1, x0, SEXT_IMM(imm); \
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)
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#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
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TEST_CASE( testnum, x0, 0, \
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li x1, val1; \
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inst x0, x1, SEXT_IMM(imm); \
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)
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#-----------------------------------------------------------------------
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# Tests for vector config instructions
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#-----------------------------------------------------------------------
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#define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
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TEST_CASE( testnum, x1, result, \
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li x1, (bank << 12); \
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vsetcfg x1,nxpr,nfpr; \
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li x1, vl; \
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vsetvl x1,x1; \
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)
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#define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \
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TEST_CASE( testnum, x1, result, \
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li x1, (bank << 12) | (nfpr << 6) | nxpr; \
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vsetcfg x1; \
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li x1, vl; \
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vsetvl x1,x1; \
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)
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#define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \
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TEST_CASE( testnum, x1, result, \
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li x1, (bank << 12); \
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vsetcfg x1,nxpr,nfpr; \
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li x1, vl; \
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vsetvl x1, x1; \
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)
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#-----------------------------------------------------------------------
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# Tests for an instruction with register operands
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#-----------------------------------------------------------------------
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#define TEST_R_OP( testnum, inst, result, val1 ) \
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TEST_CASE( testnum, x3, result, \
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li x1, val1; \
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inst x3, x1; \
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)
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#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
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TEST_CASE( testnum, x1, result, \
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li x1, val1; \
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inst x1, x1; \
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)
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#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
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TEST_CASE( testnum, x6, result, \
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li x4, 0; \
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1: li x1, val1; \
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inst x3, x1; \
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TEST_INSERT_NOPS_ ## nop_cycles \
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addi x6, x3, 0; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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)
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#-----------------------------------------------------------------------
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# Tests for an instruction with register-register operands
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#-----------------------------------------------------------------------
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#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
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TEST_CASE( testnum, x3, result, \
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li x1, val1; \
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li x2, val2; \
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inst x3, x1, x2; \
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)
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#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
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TEST_CASE( testnum, x1, result, \
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li x1, val1; \
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li x2, val2; \
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inst x1, x1, x2; \
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)
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#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
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TEST_CASE( testnum, x2, result, \
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li x1, val1; \
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li x2, val2; \
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inst x2, x1, x2; \
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)
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#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
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TEST_CASE( testnum, x1, result, \
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li x1, val1; \
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inst x1, x1, x1; \
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)
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#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
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TEST_CASE( testnum, x6, result, \
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li x4, 0; \
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1: li x1, val1; \
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li x2, val2; \
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inst x3, x1, x2; \
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TEST_INSERT_NOPS_ ## nop_cycles \
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addi x6, x3, 0; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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)
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#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
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TEST_CASE( testnum, x3, result, \
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li x4, 0; \
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1: li x1, val1; \
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TEST_INSERT_NOPS_ ## src1_nops \
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li x2, val2; \
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TEST_INSERT_NOPS_ ## src2_nops \
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inst x3, x1, x2; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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)
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#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
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TEST_CASE( testnum, x3, result, \
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li x4, 0; \
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1: li x2, val2; \
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TEST_INSERT_NOPS_ ## src1_nops \
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li x1, val1; \
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TEST_INSERT_NOPS_ ## src2_nops \
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inst x3, x1, x2; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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)
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#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
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TEST_CASE( testnum, x2, result, \
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li x1, val; \
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inst x2, x0, x1; \
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)
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#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
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TEST_CASE( testnum, x2, result, \
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li x1, val; \
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inst x2, x1, x0; \
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)
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#define TEST_RR_ZEROSRC12( testnum, inst, result ) \
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TEST_CASE( testnum, x1, result, \
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inst x1, x0, x0; \
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)
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#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
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TEST_CASE( testnum, x0, 0, \
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li x1, val1; \
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li x2, val2; \
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inst x0, x1, x2; \
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)
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#-----------------------------------------------------------------------
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# Test memory instructions
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#-----------------------------------------------------------------------
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#define TEST_LD_OP( testnum, inst, result, offset, base ) \
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TEST_CASE( testnum, x3, result, \
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la x1, base; \
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inst x3, offset(x1); \
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)
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#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
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TEST_CASE( testnum, x3, result, \
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la x1, base; \
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li x2, result; \
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store_inst x2, offset(x1); \
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load_inst x3, offset(x1); \
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)
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#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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li x4, 0; \
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1: la x1, base; \
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inst x3, offset(x1); \
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TEST_INSERT_NOPS_ ## nop_cycles \
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addi x6, x3, 0; \
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li x29, result; \
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bne x6, x29, fail; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b; \
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#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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li x4, 0; \
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1: la x1, base; \
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TEST_INSERT_NOPS_ ## nop_cycles \
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inst x3, offset(x1); \
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li x29, result; \
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bne x3, x29, fail; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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li x4, 0; \
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1: li x1, result; \
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TEST_INSERT_NOPS_ ## src1_nops \
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la x2, base; \
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TEST_INSERT_NOPS_ ## src2_nops \
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store_inst x1, offset(x2); \
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load_inst x3, offset(x2); \
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li x29, result; \
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bne x3, x29, fail; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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li x4, 0; \
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1: la x2, base; \
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TEST_INSERT_NOPS_ ## src1_nops \
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li x1, result; \
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TEST_INSERT_NOPS_ ## src2_nops \
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store_inst x1, offset(x2); \
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load_inst x3, offset(x2); \
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li x29, result; \
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bne x3, x29, fail; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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#-----------------------------------------------------------------------
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# Test branch instructions
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#-----------------------------------------------------------------------
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#define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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li x1, val1; \
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inst x1, 2f; \
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bne x0, TESTNUM, fail; \
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1: bne x0, TESTNUM, 3f; \
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2: inst x1, 1b; \
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bne x0, TESTNUM, fail; \
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3:
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#define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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li x1, val1; \
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inst x1, 1f; \
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bne x0, TESTNUM, 2f; \
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1: bne x0, TESTNUM, fail; \
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2: inst x1, 1b; \
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3:
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#define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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li x4, 0; \
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1: li x1, val1; \
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TEST_INSERT_NOPS_ ## nop_cycles \
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inst x1, fail; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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li x1, val1; \
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li x2, val2; \
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inst x1, x2, 2f; \
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bne x0, TESTNUM, fail; \
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1: bne x0, TESTNUM, 3f; \
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2: inst x1, x2, 1b; \
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bne x0, TESTNUM, fail; \
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3:
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#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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li x1, val1; \
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li x2, val2; \
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inst x1, x2, 1f; \
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bne x0, TESTNUM, 2f; \
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1: bne x0, TESTNUM, fail; \
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2: inst x1, x2, 1b; \
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3:
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#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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li x4, 0; \
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1: li x1, val1; \
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TEST_INSERT_NOPS_ ## src1_nops \
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li x2, val2; \
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TEST_INSERT_NOPS_ ## src2_nops \
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inst x1, x2, fail; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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li x4, 0; \
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1: li x2, val2; \
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TEST_INSERT_NOPS_ ## src1_nops \
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li x1, val1; \
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TEST_INSERT_NOPS_ ## src2_nops \
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inst x1, x2, fail; \
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addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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#-----------------------------------------------------------------------
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# Test jump instructions
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#-----------------------------------------------------------------------
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#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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li x4, 0; \
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1: la x6, 2f; \
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TEST_INSERT_NOPS_ ## nop_cycles \
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inst x6; \
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bne x0, TESTNUM, fail; \
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2: addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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li x4, 0; \
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1: la x6, 2f; \
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TEST_INSERT_NOPS_ ## nop_cycles \
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inst x19, x6, 0; \
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bne x0, TESTNUM, fail; \
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2: addi x4, x4, 1; \
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li x5, 2; \
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bne x4, x5, 1b \
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#-----------------------------------------------------------------------
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# RV64UF MACROS
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#-----------------------------------------------------------------------
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#-----------------------------------------------------------------------
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# Tests floating-point instructions
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#-----------------------------------------------------------------------
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#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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la a0, test_ ## testnum ## _data ;\
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flw f0, 0(a0); \
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flw f1, 4(a0); \
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flw f2, 8(a0); \
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lw a3, 12(a0); \
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code; \
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fsflags a1, x0; \
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li a2, flags; \
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bne a0, a3, fail; \
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bne a1, a2, fail; \
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j 2f; \
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.align 2; \
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.data; \
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test_ ## testnum ## _data: \
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.float val1; \
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.float val2; \
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.float val3; \
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.result; \
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.text; \
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2:
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#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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la a0, test_ ## testnum ## _data ;\
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fld f0, 0(a0); \
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fld f1, 8(a0); \
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fld f2, 16(a0); \
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ld a3, 24(a0); \
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code; \
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|
fsflags a1, x0; \
|
|
li a2, flags; \
|
|
bne a0, a3, fail; \
|
|
bne a1, a2, fail; \
|
|
j 2f; \
|
|
.data; \
|
|
.align 3; \
|
|
test_ ## testnum ## _data: \
|
|
.double val1; \
|
|
.double val2; \
|
|
.double val3; \
|
|
.result; \
|
|
.text; \
|
|
2:
|
|
|
|
#define TEST_FCVT_S_D( testnum, result, val1 ) \
|
|
TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
|
|
fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
|
|
|
|
#define TEST_FCVT_D_S( testnum, result, val1 ) \
|
|
TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
|
|
fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
|
|
|
|
#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
|
|
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \
|
|
inst f3, f0; fmv.x.s a0, f3)
|
|
|
|
#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \
|
|
TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
|
|
inst f3, f0; fmv.x.d a0, f3)
|
|
|
|
#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
|
|
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
|
|
inst f3, f0, f1; fmv.x.s a0, f3)
|
|
|
|
#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
|
|
TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
|
|
inst f3, f0, f1; fmv.x.d a0, f3)
|
|
|
|
#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
|
|
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
|
|
inst f3, f0, f1, f2; fmv.x.s a0, f3)
|
|
|
|
#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
|
|
TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \
|
|
inst f3, f0, f1, f2; fmv.x.d a0, f3)
|
|
|
|
#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
|
|
TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
|
|
inst a0, f0, rm)
|
|
|
|
#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
|
|
TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
|
|
inst a0, f0, rm)
|
|
|
|
#define TEST_FP_CMP_OP_S( testnum, inst, result, val1, val2 ) \
|
|
TEST_FP_OP_S_INTERNAL( testnum, 0, word result, val1, val2, 0.0, \
|
|
inst a0, f0, f1)
|
|
|
|
#define TEST_FP_CMP_OP_D( testnum, inst, result, val1, val2 ) \
|
|
TEST_FP_OP_D_INTERNAL( testnum, 0, dword result, val1, val2, 0.0, \
|
|
inst a0, f0, f1)
|
|
|
|
#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
|
|
test_ ## testnum: \
|
|
li TESTNUM, testnum; \
|
|
la a0, test_ ## testnum ## _data ;\
|
|
lw a3, 0(a0); \
|
|
li a0, val1; \
|
|
inst f0, a0; \
|
|
fsflags x0; \
|
|
fmv.x.s a0, f0; \
|
|
bne a0, a3, fail; \
|
|
j 1f; \
|
|
.align 2; \
|
|
test_ ## testnum ## _data: \
|
|
.float result; \
|
|
1:
|
|
|
|
#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
|
|
test_ ## testnum: \
|
|
li TESTNUM, testnum; \
|
|
la a0, test_ ## testnum ## _data ;\
|
|
ld a3, 0(a0); \
|
|
li a0, val1; \
|
|
inst f0, a0; \
|
|
fsflags x0; \
|
|
fmv.x.d a0, f0; \
|
|
bne a0, a3, fail; \
|
|
j 1f; \
|
|
.align 3; \
|
|
test_ ## testnum ## _data: \
|
|
.double result; \
|
|
1:
|
|
|
|
#-----------------------------------------------------------------------
|
|
# Pass and fail code (assumes test num is in TESTNUM)
|
|
#-----------------------------------------------------------------------
|
|
|
|
#define TEST_PASSFAIL \
|
|
bne x0, TESTNUM, pass; \
|
|
fail: \
|
|
RVTEST_FAIL; \
|
|
pass: \
|
|
RVTEST_PASS \
|
|
|
|
|
|
#-----------------------------------------------------------------------
|
|
# Test data section
|
|
#-----------------------------------------------------------------------
|
|
|
|
#define TEST_DATA
|
|
|
|
#endif
|