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33 lines
849 B
Systemverilog
33 lines
849 B
Systemverilog
module cpu_i2c (
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if_system.sys system_if,
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if_cpu_bus_out cpu_bus_if,
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if_cpu_bus_in cpu_i2c_if,
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inout scl,
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inout sda
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);
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// wire request;
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// reg ack;
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// // reg led_value;
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// assign request = (cpu_bus_if.address[31:3] == (32'h8001_0000 >> 3)) && cpu_bus_if.req;
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// assign cpu_led_if.ack = ack & request;
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// assign cpu_led_if.rdata = cpu_led_if.ack ? {32'd0} : 32'd0;
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// always_ff @(posedge system_if.clk) begin
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// ack <= 1'b0;
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// // led <= led_value;
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// if (system_if.reset) begin
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// // led_value <= 1'b0;
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// end else if (request) begin
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// ack <= 1'b1;
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// if (cpu_bus_if.wstrb[0]) begin
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// // led_value <= cpu_bus_if.wdata[0];
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// end
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// end
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// end
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endmodule
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