mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-25 23:24:15 +01:00
457 lines
12 KiB
Systemverilog
457 lines
12 KiB
Systemverilog
module memory_dma (
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input clk,
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input reset,
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dma_scb.dma dma_scb,
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fifo_bus.controller fifo_bus,
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mem_bus.controller mem_bus
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);
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// logic stop_requested;
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// logic dma_done;
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// always_ff @(posedge clk) begin
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// if (reset) begin
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// dma_scb.busy <= 1'b0;
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// stop_requested <= 1'b0;
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// end else begin
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// if (dma_scb.start) begin
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// dma_scb.busy <= 1'b1;
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// end
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// if (dma_scb.busy && dma_scb.stop) begin
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// stop_requested <= 1'b1;
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// end
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// if (dma_done) begin
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// dma_scb.busy <= 1'b0;
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// stop_requested <= 1'b0;
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// end
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// end
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// end
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// logic unaligned_start;
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// logic unaligned_end;
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// always_ff @(posedge clk) begin
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// if (dma_scb.start) begin
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// unaligned_start <= dma_scb.starting_address[0];
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// // unaligned_end <= ;
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// end
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// end
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// logic [26:0] bytes_remaining;
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// always_ff @(posedge clk) begin
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// bytes_remaining <= bytes_remaining - 27'd1;
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// if (dma_scb.start) begin
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// bytes_remaining <= dma_scb.transfer_length;
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// end
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// end
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// logic mem_transfer_request;
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// logic mem_wdata_buffer_ready;
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// logic mem_rdata_buffer_ready;
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// logic [15:0] mem_wdata_buffer;
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// logic [15:0] mem_rdata_buffer;
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// logic [1:0] mem_wdata_buffer_valid_bytes;
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// logic mem_rdata_buffer_valid;
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// always_comb begin
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// mem_transfer_request = (
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// !mem_bus.request || mem_bus.ack
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// ) && (
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// mem_wdata_buffer_ready || mem_rdata_buffer_ready
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// );
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// end
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// always_ff @(posedge clk) begin
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// if (dma_scb.start) begin
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// mem_bus.write <= dma_scb.direction;
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// mem_bus.address <= {dma_scb.starting_address[26:1], 1'b0};
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// mem_rdata_buffer_valid <= 1'b0;
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// end
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// if (mem_bus.ack) begin
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// mem_bus.request <= 1'b0;
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// mem_bus.address <= mem_bus.address + 27'd2;
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// mem_rdata_buffer <= mem_bus.rdata;
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// mem_rdata_buffer_valid <= 1'b1;
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// end
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// if (reset) begin
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// mem_bus.request <= 1'b0;
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// end else if (mem_transfer_request) begin
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// mem_bus.request <= 1'b1;
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// mem_bus.wmask <= mem_wdata_buffer_valid_bytes;
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// end
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// if (!mem_bus.request || mem_bus.ack) begin
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// if (mem_wdata_buffer_ready) begin
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// if (dma_scb.byte_swap) begin
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// mem_bus.wdata[15:8] <= mem_wdata_buffer[7:0];
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// mem_bus.wdata[7:0] <= mem_wdata_buffer[15:8];
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// end else begin
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// mem_bus.wdata <= mem_wdata_buffer;
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// end
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// end
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// end
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// end
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// // always_ff @(posedge clk) begin
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// // mem_wdata_buffer_ready <= dma_scb.busy;
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// // mem_wdata_buffer_valid_bytes <= 2'b10;
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// // end
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// logic [1:0] rx_fifo_bytes_available;
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// logic [1:0] tx_fifo_bytes_available;
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// always_comb begin
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// rx_fifo_bytes_available = 2'd2;
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// if (fifo_bus.rx_almost_empty) begin
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// rx_fifo_bytes_available = 2'd1;
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// end
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// if (fifo_bus.rx_empty) begin
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// rx_fifo_bytes_available = 2'd0;
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// end
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// tx_fifo_bytes_available = 2'd2;
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// if (fifo_bus.tx_almost_full) begin
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// tx_fifo_bytes_available = 2'd1;
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// end
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// if (fifo_bus.tx_full) begin
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// tx_fifo_bytes_available = 2'd0;
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// end
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// end
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// always_ff @(posedge clk) begin
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// if (dma_scb.busy) begin
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// if (!dma_scb.direction) begin
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// // RX FIFO handling
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// end
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// end
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// end
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// always_ff @(posedge clk) begin
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// if (dma_scb.busy) begin
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// if (dma_scb.direction) begin
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// // TX FIFO handling
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// end
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// end
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// end
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//XDDDAWDWD
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// always_ff @(posedge clk) begin
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// dma_done <= 1'b0;
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// if (dma_scb.busy && bytes_remaining == 27'd0) begin
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// // dma_done <= 1'b1;
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// end
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// end
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// typedef enum bit [1:0] {
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// } e_rx_fifo_state;
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// typedef enum bit [1:0] {
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// } e_tx_fifo_state;
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// typedef enum bit [1:0] {
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// MEM_BUS_IDLE = 2'b00,
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// MEM_BUS_WAIT = 2'b01,
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// MEM_BUS_TRANSFERRING = 2'b10,
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// } e_mem_bus_state;
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// e_mem_bus_state mem_bus_state;
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// e_mem_bus_state next_mem_bus_state;
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// always_ff @(posedge clk) begin
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// mem_bus_state <= next_mem_bus_state;
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// if (reset) begin
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// mem_bus_state <= MEM_BUS_IDLE;
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// end
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// end
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// always_comb begin
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// next_mem_bus_state = mem_bus_state;
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// case (mem_bus_state)
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// MEM_BUS_IDLE: begin
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// if (dma_scb.start) begin
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// next_mem_bus_state = MEM_BUS_WAIT;
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// end
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// end
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// MEM_BUS_WAIT: begin
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// i
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// end
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// MEM_BUS_TRANSFERRING: begin
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// end
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// endcase
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// end
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// DMA start/stop control
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logic dma_start;
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logic dma_stop;
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logic dma_stop_requested;
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always_comb begin
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dma_start = dma_scb.start && !dma_scb.stop && !dma_scb.busy;
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dma_stop = dma_scb.stop;
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end
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always_ff @(posedge clk) begin
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if (reset) begin
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dma_stop_requested <= 1'b0;
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end else begin
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if (dma_stop) begin
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dma_stop_requested <= 1'b1;
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end
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if (dma_start) begin
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dma_stop_requested <= 1'b0;
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end
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end
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end
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// Remaining counter and FIFO enable
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logic [26:0] remaining;
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logic trx_enabled;
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always_comb begin
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trx_enabled = remaining > 27'd0;
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end
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// RX FIFO controller
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logic [1:0] rx_wmask;
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logic rx_rdata_pop;
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logic rx_rdata_shift;
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logic rx_rdata_valid;
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logic [15:0] rx_buffer;
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logic rx_buffer_valid;
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logic [1:0] rx_buffer_counter;
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logic [1:0] rx_buffer_valid_counter;
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always_comb begin
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rx_buffer_valid = rx_buffer_valid_counter == 2'd2;
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end
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always_ff @(posedge clk) begin
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rx_rdata_pop <= (
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!rx_rdata_pop &&
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!fifo_bus.rx_read &&
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trx_enabled &&
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rx_buffer_counter < 2'd2 &&
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!fifo_bus.rx_empty &&
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mem_bus.write
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);
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rx_rdata_shift <= 1'b0;
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fifo_bus.rx_read <= rx_rdata_pop;
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rx_rdata_valid <= fifo_bus.rx_read;
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if (dma_start) begin
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if (dma_scb.starting_address[0]) begin
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rx_wmask <= 2'b01;
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rx_buffer_counter <= 2'd1;
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rx_buffer_valid_counter <= 2'd1;
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end else begin
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rx_wmask <= 2'b11;
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rx_buffer_counter <= 2'd0;
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rx_buffer_valid_counter <= 2'd0;
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end
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end
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if (rx_rdata_pop) begin
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rx_buffer_counter <= rx_buffer_counter + 1'd1;
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end
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if (rx_rdata_shift || rx_rdata_valid) begin
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if (dma_scb.byte_swap) begin
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rx_buffer <= {fifo_bus.rx_rdata, rx_buffer[15:8]};
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end else begin
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rx_buffer <= {rx_buffer[7:0], fifo_bus.rx_rdata};
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end
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rx_buffer_valid_counter <= rx_buffer_valid_counter + 1'd1;
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if (remaining == 27'd0 && rx_buffer_counter == 2'd1) begin
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rx_wmask <= 2'b10;
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rx_rdata_shift <= 1'b1;
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rx_buffer_counter <= rx_buffer_counter + 1'd1;
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end
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end
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if (rx_buffer_valid && !mem_bus.request) begin
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rx_wmask <= 2'b11;
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rx_buffer_counter <= 2'd0;
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rx_buffer_valid_counter <= 2'd0;
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end
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end
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// TX FIFO controller
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logic tx_wdata_push;
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logic tx_wdata_first_push;
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logic [7:0] tx_buffer;
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logic tx_buffer_counter;
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logic tx_buffer_ready;
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logic tx_buffer_valid;
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always_comb begin
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fifo_bus.tx_write = tx_wdata_push;
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end
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always_ff @(posedge clk) begin
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tx_wdata_push <= (
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!tx_wdata_push &&
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trx_enabled &&
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tx_buffer_valid &&
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!fifo_bus.tx_full &&
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!mem_bus.write
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);
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if (reset || dma_stop) begin
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tx_buffer_ready <= 1'b0;
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tx_buffer_valid <= 1'b0;
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end
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if (dma_start) begin
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tx_wdata_first_push <= 1'b1;
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tx_buffer_ready <= 1'b1;
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tx_buffer_valid <= 1'b0;
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end
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if (tx_buffer_ready && mem_bus.request) begin
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tx_buffer_ready <= 1'b0;
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end
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if (mem_bus.ack) begin
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tx_wdata_first_push <= 1'b0;
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tx_buffer_counter <= 1'd1;
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tx_buffer_valid <= 1'b1;
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{fifo_bus.tx_wdata, tx_buffer} <= mem_bus.rdata;
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if (tx_wdata_first_push && dma_scb.starting_address[0]) begin
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fifo_bus.tx_wdata <= mem_bus.rdata[7:0];
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tx_buffer_counter <= 1'd0;
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end
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end
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if (tx_wdata_push) begin
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tx_buffer_counter <= tx_buffer_counter - 1'd1;
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fifo_bus.tx_wdata <= tx_buffer;
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if (tx_buffer_counter == 1'd0) begin
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tx_buffer_ready <= 1'b1;
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tx_buffer_valid <= 1'b0;
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end
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end
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end
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// Remaining counter controller
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always_ff @(posedge clk) begin
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if (reset || dma_stop) begin
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remaining <= 27'd0;
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end else begin
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if (dma_start) begin
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remaining <= dma_scb.transfer_length;
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end
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if (!dma_stop_requested && ((mem_bus.write && rx_rdata_pop) || (!mem_bus.write && tx_wdata_push))) begin
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remaining <= remaining - 1'd1;
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end
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end
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end
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// Mem bus controller
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always_ff @(posedge clk) begin
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dma_scb.busy <= mem_bus.request || trx_enabled;
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end
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always_ff @(posedge clk) begin
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if (reset) begin
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mem_bus.request <= 1'b0;
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end else begin
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if (!mem_bus.request) begin
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if (mem_bus.write) begin
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if (rx_buffer_valid) begin
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mem_bus.request <= 1'b1;
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mem_bus.wmask <= rx_wmask;
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mem_bus.wdata <= rx_buffer;
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end
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end else begin
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if (tx_buffer_ready) begin
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mem_bus.request <= 1'b1;
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end
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end
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end
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end
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if (mem_bus.ack) begin
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mem_bus.request <= 1'b0;
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end
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end
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always_ff @(posedge clk) begin
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if (dma_start) begin
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mem_bus.write <= dma_scb.direction;
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end
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end
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always_ff @(posedge clk) begin
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if (dma_start) begin
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mem_bus.address <= {dma_scb.starting_address[26:1], 1'b0};
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end
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if (mem_bus.ack) begin
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mem_bus.address <= mem_bus.address + 27'd2;
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end
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end
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endmodule
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