mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-28 16:34:14 +01:00
211 lines
7.6 KiB
C
211 lines
7.6 KiB
C
#ifndef FPGA_H__
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#define FPGA_H__
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#include <stddef.h>
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#include <stdint.h>
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typedef enum {
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CMD_IDENTIFY,
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CMD_REG_READ,
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CMD_REG_WRITE,
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CMD_MEM_READ,
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CMD_MEM_WRITE,
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CMD_USB_STATUS,
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CMD_USB_READ,
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CMD_USB_WRITE
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} fpga_cmd_t;
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typedef enum {
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REG_MEM_ADDRESS,
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REG_MEM_SCR,
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REG_USB_SCR,
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REG_USB_DMA_ADDRESS,
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REG_USB_DMA_LENGTH,
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REG_USB_DMA_SCR,
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REG_CFG_SCR,
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REG_CFG_DATA_0,
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REG_CFG_DATA_1,
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REG_CFG_CMD,
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REG_CFG_IDENTIFIER,
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REG_FLASHRAM_SCR,
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REG_FLASH_SCR,
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REG_RTC_SCR,
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REG_RTC_TIME_0,
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REG_RTC_TIME_1,
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REG_SD_SCR,
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REG_SD_ARG,
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REG_SD_CMD,
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REG_SD_RSP_0,
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REG_SD_RSP_1,
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REG_SD_RSP_2,
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REG_SD_RSP_3,
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REG_SD_DAT,
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REG_SD_DMA_ADDRESS,
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REG_SD_DMA_LENGTH,
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REG_SD_DMA_SCR,
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REG_DD_SCR,
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REG_DD_CMD_DATA,
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REG_DD_HEAD_TRACK,
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REG_DD_SECTOR_INFO,
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REG_DD_DRIVE_ID,
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REG_SAVE_COUNT,
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REG_VENDOR_SCR,
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REG_VENDOR_DATA,
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REG_DEBUG_0,
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REG_DEBUG_1,
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REG_CIC_0,
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REG_CIC_1,
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} fpga_reg_t;
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#define ALIGN(value, align) (((value) + ((typeof(value))(align) - 1)) & ~((typeof(value))(align) - 1))
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#define SWAP16(x) ((((x) & 0xFF) << 8) | (((x) & 0xFF00) >> 8))
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#define SWAP32(x) (((x) & 0xFF) << 24 | ((x) & 0xFF00) << 8 | ((x) & 0xFF0000) >> 8 | ((x) & 0xFF000000) >> 24)
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#define FPGA_ID (0x64)
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#define FPGA_MAX_MEM_TRANSFER (1024)
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#define USB_STATUS_RXNE (1 << 0)
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#define USB_STATUS_TXE (1 << 1)
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#define MEM_SCR_START (1 << 0)
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#define MEM_SCR_STOP (1 << 1)
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#define MEM_SCR_DIRECTION (1 << 2)
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#define MEM_SCR_BUSY (1 << 3)
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#define MEM_SCR_LENGTH_BIT (4)
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#define USB_SCR_FIFO_FLUSH (1 << 0)
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#define USB_SCR_RXNE (1 << 1)
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#define USB_SCR_TXE (1 << 2)
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#define USB_SCR_RESET_PENDING (1 << 3)
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#define USB_SCR_RESET_ACK (1 << 4)
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#define USB_SCR_WRITE_FLUSH (1 << 5)
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#define USB_SCR_RX_COUNT_BIT (6)
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#define USB_SCR_RX_COUNT_MASK (0x7FF << USB_SCR_RX_COUNT_BIT)
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#define USB_SCR_TX_COUNT_BIT (17)
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#define USB_SCR_TX_COUNT_MASK (0x7FF << USB_SCR_TX_COUNT_BIT)
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#define USB_SCR_RESET_STATE (1 << 28)
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#define USB_SCR_PWRSAV (1 << 29)
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#define DMA_SCR_START (1 << 0)
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#define DMA_SCR_STOP (1 << 1)
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#define DMA_SCR_DIRECTION (1 << 2)
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#define DMA_SCR_BUSY (1 << 3)
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#define DMA_SCR_BYTE_SWAP (1 << 4)
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#define CFG_SCR_BOOTLOADER_ENABLED (1 << 0)
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#define CFG_SCR_BOOTLOADER_SKIP (1 << 1)
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#define CFG_SCR_ROM_WRITE_ENABLED (1 << 2)
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#define CFG_SCR_ROM_SHADOW_ENABLED (1 << 3)
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#define CFG_SCR_SRAM_ENABLED (1 << 4)
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#define CFG_SCR_SRAM_BANKED (1 << 5)
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#define CFG_SCR_FLASHRAM_ENABLED (1 << 6)
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#define CFG_SCR_DD_ENABLED (1 << 7)
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#define CFG_SCR_DDIPL_ENABLED (1 << 8)
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#define CFG_SCR_EEPROM_ENABLED (1 << 9)
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#define CFG_SCR_EEPROM_16K (1 << 10)
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#define CFG_SCR_ROM_EXTENDED_ENABLED (1 << 11)
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#define CFG_SCR_BUTTON_STATE (1 << 31)
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#define CFG_CMD_BIT (0)
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#define CFG_CMD_MASK (0xFF << CFG_CMD_BIT)
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#define CFG_CMD_PENDING (1 << 8)
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#define CFG_CMD_DONE (1 << 9)
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#define CFG_CMD_ERROR (1 << 10)
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#define CFG_CMD_IRQ (1 << 11)
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#define FLASHRAM_SCR_DONE (1 << 0)
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#define FLASHRAM_SCR_PENDING (1 << 1)
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#define FLASHRAM_SCR_PAGE_BIT (2)
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#define FLASHRAM_SCR_PAGE_MASK (0x3FF << FLASHRAM_SCR_PAGE_BIT)
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#define FLASHRAM_SCR_SECTOR_OR_ALL (1 << 12)
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#define FLASHRAM_SCR_WRITE_OR_ERASE (1 << 13)
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#define FLASH_SCR_BUSY (1 << 0)
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#define RTC_SCR_PENDING (1 << 0)
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#define RTC_SCR_DONE (1 << 1)
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#define RTC_SCR_MAGIC (0x52544300)
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#define RTC_SCR_MAGIC_MASK (0xFFFFFF00)
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#define SD_SCR_CLOCK_MODE_OFF (0 << 0)
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#define SD_SCR_CLOCK_MODE_400KHZ (1 << 0)
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#define SD_SCR_CLOCK_MODE_25MHZ (2 << 0)
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#define SD_SCR_CLOCK_MODE_50MHZ (3 << 0)
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#define SD_SCR_CLOCK_MODE_BIT (0)
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#define SD_SCR_CLOCK_MODE_MASK (0x3 << SD_SCR_CLOCK_MODE_BIT)
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#define SD_SCR_CMD_BUSY (1 << 2)
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#define SD_SCR_CMD_ERROR (1 << 3)
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#define SD_SCR_CARD_BUSY (1 << 4)
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#define SD_SCR_CARD_INSERTED (1 << 5)
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#define SD_SCR_RX_COUNT_BIT (6)
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#define SD_SCR_RX_COUNT_MASK (0x7FF << SD_SCR_RX_COUNT_BIT)
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#define SD_SCR_TX_COUNT_BIT (17)
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#define SD_SCR_TX_COUNT_MASK (0x7FF << SD_SCR_TX_COUNT_BIT)
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#define SD_CMD_INDEX_BIT (0)
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#define SD_CMD_INDEX_MASK (0x3F)
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#define SD_CMD_SKIP_RESPONSE (1 << 6)
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#define SD_CMD_RESERVED_RESPONSE (1 << 7)
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#define SD_CMD_LONG_RESPONSE (1 << 8)
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#define SD_CMD_IGNORE_CRC (1 << 9)
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#define SD_DAT_FIFO_FLUSH (1 << 0)
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#define SD_DAT_START_WRITE (1 << 1)
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#define SD_DAT_START_READ (1 << 2)
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#define SD_DAT_STOP (1 << 3)
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#define SD_DAT_BLOCKS_BIT (4)
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#define SD_DAT_BLOCKS_MASK (0xFF << SD_DAT_BLOCKS_BIT)
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#define SD_DAT_BUSY (1 << 12)
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#define SD_DAT_ERROR (1 << 13)
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#define DD_SCR_HARD_RESET (1 << 0)
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#define DD_SCR_HARD_RESET_CLEAR (1 << 1)
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#define DD_SCR_CMD_PENDING (1 << 2)
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#define DD_SCR_CMD_READY (1 << 3)
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#define DD_SCR_BM_PENDING (1 << 4)
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#define DD_SCR_BM_READY (1 << 5)
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#define DD_SCR_DISK_INSERTED (1 << 6)
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#define DD_SCR_DISK_CHANGED (1 << 7)
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#define DD_SCR_BM_START (1 << 8)
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#define DD_SCR_BM_START_CLEAR (1 << 9)
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#define DD_SCR_BM_STOP (1 << 10)
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#define DD_SCR_BM_STOP_CLEAR (1 << 11)
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#define DD_SCR_BM_TRANSFER_MODE (1 << 12)
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#define DD_SCR_BM_TRANSFER_BLOCKS (1 << 13)
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#define DD_SCR_BM_TRANSFER_DATA (1 << 14)
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#define DD_SCR_BM_TRANSFER_C2 (1 << 15)
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#define DD_SCR_BM_MICRO_ERROR (1 << 16)
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#define DD_SCR_BM_ACK (1 << 17)
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#define DD_SCR_BM_ACK_CLEAR (1 << 18)
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#define DD_SCR_BM_CLEAR (1 << 19)
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#define DD_TRACK_MASK (0x0FFF)
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#define DD_HEAD_MASK (0x1000)
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#define DD_HEAD_TRACK_MASK (DD_HEAD_MASK | DD_TRACK_MASK)
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#define DD_HEAD_TRACK_INDEX_LOCK (1 << 13)
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#define CIC_SEED_BIT (16)
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#define CIC_REGION (1 << 24)
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#define CIC_64DD_MODE (1 << 25)
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#define CIC_DISABLED (1 << 26)
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#define CIC_INVALID_REGION_DETECTED (1 << 27)
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#define CIC_INVALID_REGION_RESET (1 << 28)
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uint8_t fpga_id_get (void);
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uint32_t fpga_reg_get (fpga_reg_t reg);
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void fpga_reg_set (fpga_reg_t reg, uint32_t value);
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void fpga_mem_read (uint32_t address, size_t length, uint8_t *buffer);
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void fpga_mem_write (uint32_t address, size_t length, uint8_t *buffer);
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void fpga_mem_copy (uint32_t src, uint32_t dst, size_t length);
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uint8_t fpga_usb_status_get (void);
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uint8_t fpga_usb_pop (void);
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void fpga_usb_push (uint8_t data);
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#endif
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