mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-24 12:01:56 +01:00
139 lines
4.9 KiB
Systemverilog
139 lines
4.9 KiB
Systemverilog
module n64_cfg (
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input clk,
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input reset,
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n64_reg_bus.cfg reg_bus,
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n64_scb.cfg n64_scb,
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output logic irq
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);
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typedef enum bit [3:0] {
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REG_STATUS,
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REG_COMMAND,
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REG_DATA_0_H,
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REG_DATA_0_L,
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REG_DATA_1_H,
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REG_DATA_1_L,
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REG_IDENTIFIER_H,
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REG_IDENTIFIER_L,
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REG_KEY_H,
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REG_KEY_L
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} e_reg;
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logic cfg_error;
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always_comb begin
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reg_bus.rdata = 16'd0;
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if (reg_bus.address[16] && (reg_bus.address[15:5] == 11'd0)) begin
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case (reg_bus.address[4:1])
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REG_STATUS: reg_bus.rdata = {
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n64_scb.cfg_pending,
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cfg_error,
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irq,
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13'd0
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};
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REG_COMMAND: reg_bus.rdata = {8'd0, n64_scb.cfg_cmd};
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REG_DATA_0_H: reg_bus.rdata = n64_scb.cfg_wdata[0][31:16];
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REG_DATA_0_L: reg_bus.rdata = n64_scb.cfg_wdata[0][15:0];
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REG_DATA_1_H: reg_bus.rdata = n64_scb.cfg_wdata[1][31:16];
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REG_DATA_1_L: reg_bus.rdata = n64_scb.cfg_wdata[1][15:0];
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REG_IDENTIFIER_H: reg_bus.rdata = n64_scb.cfg_identifier[31:16];
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REG_IDENTIFIER_L: reg_bus.rdata = n64_scb.cfg_identifier[15:0];
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REG_KEY_H: reg_bus.rdata = 16'd0;
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REG_KEY_L: reg_bus.rdata = 16'd0;
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endcase
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end
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end
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logic unlock_flag;
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logic lock_sequence_counter;
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always_ff @(posedge clk) begin
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if (n64_scb.cfg_done) begin
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n64_scb.cfg_pending <= 1'b0;
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cfg_error <= n64_scb.cfg_error;
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end
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if (n64_scb.cfg_irq) begin
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irq <= 1'b1;
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end
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if (unlock_flag) begin
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n64_scb.cfg_unlock <= 1'b1;
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end
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if (reset || n64_scb.n64_reset || n64_scb.n64_nmi) begin
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n64_scb.cfg_unlock <= 1'b0;
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n64_scb.cfg_pending <= 1'b0;
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n64_scb.cfg_cmd <= 8'h00;
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irq <= 1'b0;
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cfg_error <= 1'b0;
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lock_sequence_counter <= 1'd0;
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end else if (n64_scb.cfg_unlock) begin
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if (reg_bus.write && reg_bus.address[16] && (reg_bus.address[15:5] == 11'd0)) begin
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case (reg_bus.address[4:1])
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REG_COMMAND: begin
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n64_scb.cfg_pending <= 1'b1;
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n64_scb.cfg_cmd <= reg_bus.wdata[7:0];
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cfg_error <= 1'b0;
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end
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REG_DATA_0_H: n64_scb.cfg_rdata[0][31:16] <= reg_bus.wdata;
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REG_DATA_0_L: n64_scb.cfg_rdata[0][15:0] <= reg_bus.wdata;
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REG_DATA_1_H: n64_scb.cfg_rdata[1][31:16] <= reg_bus.wdata;
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REG_DATA_1_L: n64_scb.cfg_rdata[1][15:0] <= reg_bus.wdata;
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REG_IDENTIFIER_H: irq <= 1'b0;
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REG_KEY_H, REG_KEY_L: begin
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lock_sequence_counter <= lock_sequence_counter + 1'd1;
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if (reg_bus.wdata != 16'hFFFF) begin
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lock_sequence_counter <= 1'd0;
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end
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if (lock_sequence_counter == 1'd1) begin
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n64_scb.cfg_unlock <= (reg_bus.wdata != 16'hFFFF);
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end
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end
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endcase
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end
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end
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end
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const bit [15:0] UNLOCK_SEQUENCE [4] = {
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16'h5F55,
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16'h4E4C,
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16'h4F43,
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16'h4B5F
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};
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logic [1:0] unlock_sequence_counter;
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always_ff @(posedge clk) begin
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unlock_flag <= 1'b0;
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if (reset || n64_scb.n64_reset || n64_scb.n64_nmi) begin
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unlock_sequence_counter <= 2'd0;
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end else if (!n64_scb.cfg_unlock) begin
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if (reg_bus.write && reg_bus.address[16] && (reg_bus.address[15:5] == 11'd0)) begin
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case (reg_bus.address[4:1])
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REG_KEY_H, REG_KEY_L: begin
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for (int index = 0; index < $size(UNLOCK_SEQUENCE); index++) begin
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if (index == unlock_sequence_counter) begin
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if (reg_bus.wdata == UNLOCK_SEQUENCE[index]) begin
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unlock_sequence_counter <= unlock_sequence_counter + 1'd1;
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if (index == ($size(UNLOCK_SEQUENCE) - 1'd1)) begin
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unlock_flag <= 1'b1;
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unlock_sequence_counter <= 2'd0;
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end
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end else begin
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unlock_sequence_counter <= 2'd0;
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end
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end
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end
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end
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endcase
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end
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end
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end
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endmodule
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