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https://github.com/Polprzewodnikowy/SummerCart64.git
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99 lines
2.1 KiB
Systemverilog
99 lines
2.1 KiB
Systemverilog
module n64_soc (
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if_system sys,
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if_config cfg,
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if_dma.memory dma,
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if_sdram.memory sdram,
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if_flashram.flashram flashram,
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if_si.si si,
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if_flash.memory flash,
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if_dd dd,
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if_cpu_ram.external cpu_ram,
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input n64_pi_alel,
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input n64_pi_aleh,
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input n64_pi_read,
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input n64_pi_write,
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inout [15:0] n64_pi_ad,
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input n64_si_clk,
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inout n64_si_dq,
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output sdram_cs,
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output sdram_ras,
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output sdram_cas,
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output sdram_we,
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output [1:0] sdram_ba,
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output [12:0] sdram_a,
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inout [15:0] sdram_dq
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);
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if_n64_bus bus ();
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n64_pi n64_pi_inst (
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.sys(sys),
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.cfg(cfg),
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.bus(bus),
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.n64_pi_alel(n64_pi_alel),
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.n64_pi_aleh(n64_pi_aleh),
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.n64_pi_read(n64_pi_read),
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.n64_pi_write(n64_pi_write),
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.n64_pi_ad(n64_pi_ad)
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);
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n64_si n64_si_inst (
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.sys(sys),
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.si(si),
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.n64_si_clk(n64_si_clk),
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.n64_si_dq(n64_si_dq)
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);
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n64_sdram n64_sdram_inst (
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.sys(sys),
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.bus(bus.at[sc64::ID_N64_SDRAM].device),
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.dma(dma),
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.sdram(sdram),
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.sdram_cs(sdram_cs),
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.sdram_ras(sdram_ras),
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.sdram_cas(sdram_cas),
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.sdram_we(sdram_we),
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.sdram_ba(sdram_ba),
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.sdram_a(sdram_a),
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.sdram_dq(sdram_dq)
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);
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n64_bootloader n64_bootloader_inst (
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.sys(sys),
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.bus(bus.at[sc64::ID_N64_BOOTLOADER].device),
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.flash(flash)
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);
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n64_flashram n64_flashram_inst (
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.sys(sys),
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.bus(bus.at[sc64::ID_N64_FLASHRAM].device),
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.cfg(cfg),
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.flashram(flashram)
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);
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n64_dd n64_dd_inst (
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.sys(sys),
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.bus(bus.at[sc64::ID_N64_DD].device),
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.dd(dd)
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);
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n64_dd_sector_buffer n64_dd_sector_buffer_inst (
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.sys(sys),
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.dd(dd)
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);
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n64_cfg n64_cfg_inst (
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.sys(sys),
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.bus(bus.at[sc64::ID_N64_CFG].device),
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.cfg(cfg),
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.cpu_ram(cpu_ram)
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);
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endmodule
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