mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-22 22:19:14 +01:00
250 lines
7.8 KiB
Verilog
250 lines
7.8 KiB
Verilog
module sd_cmd (
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input i_clk,
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input i_reset,
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inout io_sd_cmd,
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input i_sd_clk_strobe_rising,
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input i_sd_clk_strobe_falling,
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input [5:0] i_command_index,
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input [31:0] i_command_argument,
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input i_command_long_response,
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input i_command_skip_response,
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output reg [5:0] o_command_index,
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output reg [31:0] o_command_response,
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input i_command_start,
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output o_command_busy,
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output reg o_command_timeout,
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output reg o_command_response_crc_error
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);
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// Start synchronizer
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reg r_pending_start;
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wire w_start = r_pending_start && i_sd_clk_strobe_falling;
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always @(posedge i_clk) begin
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if (i_reset) begin
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r_pending_start <= 1'b0;
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end else begin
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if (i_command_start) begin
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r_pending_start <= 1'b1;
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end else if (i_sd_clk_strobe_falling) begin
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r_pending_start <= 1'b0;
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end
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end
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end
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// Module state
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localparam STATE_IDLE = 0;
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localparam STATE_SENDING = 1;
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localparam STATE_RESP_WAIT = 2;
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localparam STATE_RECEIVING = 3;
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localparam STATE_HIZ_WAIT = 4;
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reg [4:0] r_state;
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// Bit counter logic
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reg [8:0] r_bit_counter;
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reg r_bit_done;
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wire w_command_start = w_start && r_state[STATE_IDLE];
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wire w_command_end = r_bit_done && r_state[STATE_SENDING];
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wire w_response_timeout = r_bit_done && r_state[STATE_RESP_WAIT];
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wire w_response_start = !io_sd_cmd && i_sd_clk_strobe_rising && r_state[STATE_RESP_WAIT];
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wire w_response_end = r_bit_done && r_state[STATE_RECEIVING];
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wire w_hiz_end = r_bit_done && r_state[STATE_HIZ_WAIT];
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localparam [8:0] COMMAND_BIT_LENGTH = (9'd48 - 1'd1);
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localparam [8:0] RESPONSE_WAIT_BIT_LENGTH = (9'd64 - 1'd1);
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localparam [8:0] RESPONSE_SHORT_BIT_LENGTH = (9'd48 - 1'd1);
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localparam [8:0] RESPONSE_LONG_BIT_LENGTH = (9'd136 - 1'd1);
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localparam [8:0] HIZ_WAIT_BIT_LENGTH = (9'd8 - 1'd1);
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always @(posedge i_clk) begin
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if (w_command_start) begin
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r_bit_counter <= COMMAND_BIT_LENGTH;
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r_bit_done <= 1'b0;
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end else if (w_command_end) begin
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r_bit_counter <= RESPONSE_WAIT_BIT_LENGTH;
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r_bit_done <= 1'b0;
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end else if (w_response_start) begin
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r_bit_counter <= i_command_long_response ? RESPONSE_LONG_BIT_LENGTH : RESPONSE_SHORT_BIT_LENGTH;
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r_bit_done <= 1'b0;
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end else if (w_response_end) begin
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r_bit_counter <= HIZ_WAIT_BIT_LENGTH;
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r_bit_done <= 1'b0;
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end else if (i_sd_clk_strobe_rising) begin
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if (r_bit_counter > 9'd0) begin
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r_bit_counter <= r_bit_counter - 1'd1;
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end else begin
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r_bit_done <= 1'b1;
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end
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end
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end
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// CRC7 generator
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reg [6:0] r_crc_7_received;
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wire w_crc_shift_reset = !(r_state[STATE_SENDING] || r_state[STATE_RECEIVING]);
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wire w_crc_shift_enabled = (r_bit_counter <= 9'd127) && (r_bit_counter > (r_state[STATE_SENDING] ? 9'd7 : 9'd8));
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wire w_crc_shift = w_crc_shift_enabled && i_sd_clk_strobe_rising;
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wire [6:0] w_crc_7_calculated;
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sd_crc_7 sd_crc_7_inst (
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.i_clk(i_clk),
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.i_crc_reset(w_crc_shift_reset),
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.i_crc_shift(w_crc_shift),
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.i_crc_input(io_sd_cmd),
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.o_crc_output(w_crc_7_calculated)
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);
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// Control signals
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assign o_command_busy = r_pending_start || (!r_state[STATE_IDLE]);
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always @(posedge i_clk) begin
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if (i_reset) begin
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o_command_timeout <= 1'b0;
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o_command_response_crc_error <= 1'b0;
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end else begin
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if (w_command_start) begin
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o_command_timeout <= 1'b0;
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end
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if (w_response_timeout) begin
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o_command_timeout <= 1'b1;
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end
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if (w_response_end) begin
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o_command_response_crc_error <= (w_crc_7_calculated != r_crc_7_received);
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end
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end
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end
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// State machine
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always @(posedge i_clk) begin
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if (i_reset) begin
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r_state <= (1'b1 << STATE_IDLE);
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end else begin
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r_state <= 5'b00000;
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unique case (1'b1)
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r_state[STATE_IDLE]: begin
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if (w_start) begin
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r_state[STATE_SENDING] <= 1'b1;
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end else begin
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r_state[STATE_IDLE] <= 1'b1;
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end
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end
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r_state[STATE_SENDING]: begin
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if (w_command_end) begin
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if (i_command_skip_response) begin
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r_state[STATE_HIZ_WAIT] <= 1'b1;
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end else begin
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r_state[STATE_RESP_WAIT] <= 1'b1;
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end
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end else begin
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r_state[STATE_SENDING] <= 1'b1;
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end
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end
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r_state[STATE_RESP_WAIT]: begin
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if (w_response_timeout) begin
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r_state[STATE_IDLE] <= 1'b1;
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end else if (w_response_start) begin
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r_state[STATE_RECEIVING] <= 1'b1;
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end else begin
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r_state[STATE_RESP_WAIT] <= 1'b1;
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end
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end
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r_state[STATE_RECEIVING]: begin
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if (w_response_end) begin
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r_state[STATE_HIZ_WAIT] <= 1'b1;
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end else begin
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r_state[STATE_RECEIVING] <= 1'b1;
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end
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end
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r_state[STATE_HIZ_WAIT]: begin
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if (w_hiz_end) begin
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r_state[STATE_IDLE] <= 1'b1;
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end else begin
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r_state[STATE_HIZ_WAIT] <= 1'b1;
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end
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end
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endcase
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end
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end
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// Shifting operation
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reg [7:0] r_shift;
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wire w_shift = (r_state[STATE_SENDING] && i_sd_clk_strobe_falling) || (r_state[STATE_RECEIVING] && i_sd_clk_strobe_rising);
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assign io_sd_cmd = r_state[STATE_SENDING] ? r_shift[7] : 1'bZ;
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always @(posedge i_clk) begin
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if (w_command_start) begin
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o_command_response <= 32'h0000_0000;
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r_shift <= {2'b01, i_command_index};
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end else if (w_response_start) begin
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r_shift <= 8'h00;
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end else begin
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if (w_shift) begin
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r_shift <= {r_shift[6:0], io_sd_cmd};
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end
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if (i_sd_clk_strobe_falling && r_state[STATE_SENDING]) begin
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if (r_bit_counter == 9'd39) begin
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r_shift <= i_command_argument[31:24];
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end
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if (r_bit_counter == 9'd31) begin
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r_shift <= i_command_argument[23:16];
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end
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if (r_bit_counter == 9'd23) begin
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r_shift <= i_command_argument[15:8];
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end
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if (r_bit_counter == 9'd15) begin
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r_shift <= i_command_argument[7:0];
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end
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if (r_bit_counter == 9'd7) begin
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r_shift <= {w_crc_7_calculated, 1'b1};
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end
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end
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if (i_sd_clk_strobe_rising && r_state[STATE_RECEIVING]) begin
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if (r_bit_counter == (i_command_long_response ? 9'd128 : 9'd40)) begin
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o_command_index <= r_shift[5:0];
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end else if (r_bit_counter[2:0] == 3'd0) begin
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if (r_bit_counter > 9'd7) begin
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o_command_response <= {o_command_response[23:0], r_shift};
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end else begin
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r_crc_7_received <= r_shift[7:1];
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end
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end
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end
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end
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end
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endmodule
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