mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-25 07:06:52 +01:00
280 lines
8.5 KiB
C
280 lines
8.5 KiB
C
#ifndef IO_H__
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#define IO_H__
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#include <stddef.h>
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#include <stdint.h>
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typedef volatile uint8_t io8_t;
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typedef volatile uint32_t io32_t;
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#define ALIGN(value, align) (((value) + ((typeof(value))(align) - 1)) & ~((typeof(value))(align) - 1))
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#define PHYSICAL(address) ((typeof(address)) (((io32_t) (address)) & (0x1FFFFFFFUL)))
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#define UNCACHED(address) ((typeof(address)) (((io32_t) (address)) | (0xA0000000UL)))
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#define N64_RAM_SIZE (0x00800000UL)
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#define FROM_BCD(x) ((((x >> 4) & 0x0F) * 10) + (x & 0x0F))
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typedef struct {
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io32_t DMEM[1024];
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io32_t IMEM[1024];
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} sp_mem_t;
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#define SP_MEM_BASE (0x04000000UL)
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#define SP_MEM ((sp_mem_t *) SP_MEM_BASE)
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typedef struct {
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io32_t PADDR;
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io32_t MADDR;
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io32_t RD_LEN;
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io32_t WR_LEN;
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io32_t SR;
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io32_t DMA_FULL;
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io32_t DMA_BUSY;
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io32_t SEMAPHORE;
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io32_t __reserved[0xFFF8];
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io32_t PC;
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} sp_regs_t;
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#define SP_BASE (0x04040000UL)
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#define SP ((sp_regs_t *) SP_BASE)
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#define SP_SR_HALT (1 << 0)
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#define SP_SR_BROKE (1 << 1)
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#define SP_SR_DMA_BUSY (1 << 2)
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#define SP_SR_DMA_FULL (1 << 3)
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#define SP_SR_IO_FULL (1 << 4)
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#define SP_SR_SSTEP (1 << 5)
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#define SP_SR_INTR_BREAK (1 << 6)
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#define SP_SR_SIG0 (1 << 7)
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#define SP_SR_SIG1 (1 << 8)
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#define SP_SR_SIG2 (1 << 9)
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#define SP_SR_SIG3 (1 << 10)
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#define SP_SR_SIG4 (1 << 11)
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#define SP_SR_SIG5 (1 << 12)
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#define SP_SR_SIG6 (1 << 13)
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#define SP_SR_SIG7 (1 << 14)
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#define SP_SR_CLR_HALT (1 << 0)
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#define SP_SR_SET_HALT (1 << 1)
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#define SP_SR_CLR_BROKE (1 << 2)
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#define SP_SR_CLR_INTR (1 << 3)
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#define SP_SR_SET_INTR (1 << 4)
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#define SP_SR_CLR_SSTEP (1 << 5)
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#define SP_SR_SET_SSTEP (1 << 6)
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#define SP_SR_CLR_INTR_BREAK (1 << 7)
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#define SP_SR_SET_INTR_BREAK (1 << 8)
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#define SP_SR_CLR_SIG0 (1 << 9)
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#define SP_SR_SET_SIG0 (1 << 10)
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#define SP_SR_CLR_SIG1 (1 << 11)
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#define SP_SR_SET_SIG1 (1 << 12)
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#define SP_SR_CLR_SIG2 (1 << 13)
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#define SP_SR_SET_SIG2 (1 << 14)
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#define SP_SR_CLR_SIG3 (1 << 15)
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#define SP_SR_SET_SIG3 (1 << 16)
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#define SP_SR_CLR_SIG4 (1 << 17)
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#define SP_SR_SET_SIG4 (1 << 18)
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#define SP_SR_CLR_SIG5 (1 << 19)
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#define SP_SR_SET_SIG5 (1 << 20)
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#define SP_SR_CLR_SIG6 (1 << 21)
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#define SP_SR_SET_SIG6 (1 << 22)
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#define SP_SR_CLR_SIG7 (1 << 23)
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#define SP_SR_SET_SIG7 (1 << 24)
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typedef struct {
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io32_t START;
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io32_t END;
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io32_t CURRENT;
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io32_t SR;
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io32_t CLOCK;
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io32_t BUF_BUSY;
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io32_t PIPE_BUSY;
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io32_t TMEM;
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} dpc_regs_t;
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#define DPC_BASE (0x04100000UL)
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#define DPC ((dpc_regs_t *) DPC_BASE)
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#define DPC_SR_XBUS_DMEM_DMA (1 << 0)
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#define DPC_SR_FREEZE (1 << 1)
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#define DPC_SR_FLUSH (1 << 2)
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#define DPC_SR_START_GCLK (1 << 3)
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#define DPC_SR_TMEM_BUSY (1 << 4)
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#define DPC_SR_PIPE_BUSY (1 << 5)
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#define DPC_SR_CMD_BUSY (1 << 6)
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#define DPC_SR_CBUF_READY (1 << 7)
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#define DPC_SR_DMA_BUSY (1 << 8)
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#define DPC_SR_END_VALID (1 << 9)
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#define DPC_SR_START_VALID (1 << 10)
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#define DPC_SR_CLR_XBUS_DMEM_DMA (1 << 0)
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#define DPC_SR_SET_XBUS_DMEM_DMA (1 << 1)
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#define DPC_SR_CLR_FREEZE (1 << 2)
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#define DPC_SR_SET_FREEZE (1 << 3)
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#define DPC_SR_CLR_FLUSH (1 << 4)
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#define DPC_SR_SET_FLUSH (1 << 5)
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#define DPC_SR_CLR_TMEM_CTR (1 << 6)
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#define DPC_SR_CLR_PIPE_CTR (1 << 7)
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#define DPC_SR_CLR_CMD_CTR (1 << 8)
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#define DPC_SR_CLR_CLOCK_CTR (1 << 9)
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typedef struct {
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io32_t CR;
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io32_t MADDR;
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io32_t H_WIDTH;
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io32_t V_INTR;
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io32_t CURR_LINE;
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io32_t TIMING;
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io32_t V_SYNC;
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io32_t H_SYNC;
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io32_t H_SYNC_LEAP;
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io32_t H_LIMITS;
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io32_t V_LIMITS;
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io32_t COLOR_BURST;
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io32_t H_SCALE;
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io32_t V_SCALE;
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} vi_regs_t;
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#define VI_BASE (0x04400000UL)
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#define VI ((vi_regs_t *) VI_BASE)
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#define VI_CR_TYPE_16 (2 << 0)
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#define VI_CR_TYPE_32 (3 << 0)
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#define VI_CR_GAMMA_DITHER_ON (1 << 2)
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#define VI_CR_GAMMA_ON (1 << 3)
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#define VI_CR_DIVOT_ON (1 << 4)
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#define VI_CR_SERRATE_ON (1 << 6)
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#define VI_CR_ANTIALIAS_0 (1 << 8)
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#define VI_CR_ANTIALIAS_1 (1 << 9)
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#define VI_CR_PIXEL_ADVANCE_0 (1 << 12)
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#define VI_CR_PIXEL_ADVANCE_1 (1 << 13)
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#define VI_CR_PIXEL_ADVANCE_2 (1 << 14)
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#define VI_CR_PIXEL_ADVANCE_3 (1 << 15)
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#define VI_CR_DITHER_FILTER_ON (1 << 16)
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#define VI_CURR_LINE_FIELD (1 << 0)
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typedef struct {
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io32_t MADDR;
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io32_t LEN;
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io32_t CR;
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io32_t SR;
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io32_t DACRATE;
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io32_t BITRATE;
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} ai_regs_t;
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#define AI_BASE (0x04500000UL)
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#define AI ((ai_regs_t *) AI_BASE)
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#define AI_SR_DMA_BUSY (1 << 30)
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#define AI_SR_FIFO_FULL (1 << 31)
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#define AI_CR_DMA_ON (1 << 0)
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typedef struct {
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io32_t MADDR;
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io32_t PADDR;
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io32_t RDMA;
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io32_t WDMA;
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io32_t SR;
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struct {
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io32_t LAT;
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io32_t PWD;
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io32_t PGS;
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io32_t RLS;
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} DOM[2];
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} pi_regs_t;
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#define PI_BASE (0x04600000UL)
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#define PI ((pi_regs_t *) PI_BASE)
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#define PI_SR_DMA_BUSY (1 << 0)
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#define PI_SR_IO_BUSY (1 << 1)
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#define PI_SR_DMA_ERROR (1 << 2)
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#define PI_SR_RESET (1 << 0)
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#define PI_SR_CLR_INTR (1 << 1)
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typedef struct {
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io32_t MADDR;
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io32_t RDMA;
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io32_t __reserved_1;
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io32_t __reserved_2;
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io32_t WDMA;
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io32_t __reserved_3;
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io32_t SR;
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} si_regs_t;
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#define SI_BASE (0x04800000UL)
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#define SI ((si_regs_t *) SI_BASE)
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#define SI_SR_DMA_BUSY (1 << 0)
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#define SI_SR_IO_BUSY (1 << 1)
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#define SI_SR_DMA_ERROR (1 << 3)
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#define SI_SR_INTERRUPT (1 << 12)
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#define SI_SR_CLEAR_INTERRUPT (0)
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#define ROM_DDIPL_BASE (0x06000000UL)
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#define ROM_DDIPL ((io32_t *) ROM_DDIPL_BASE)
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#define ROM_CART_BASE (0x10000000UL)
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#define ROM_CART ((io32_t *) ROM_CART_BASE)
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#define PIFRAM_BASE (0x1FC007C0UL)
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#define PIFRAM ((io8_t *) PIFRAM_BASE)
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#define PIFRAM_STATUS (&PIFRAM[0x3C])
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#define PIFRAM_TERMINATE_BOOT (1 << 3)
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typedef struct {
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uint32_t tv_type;
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uint32_t device_type;
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uint32_t device_base;
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uint32_t reset_type;
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uint32_t cic_id;
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uint32_t version;
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uint32_t mem_size;
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uint8_t app_nmi_buffer[64];
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uint32_t __reserved_1[37];
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uint32_t mem_size_6105;
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} os_info_t;
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#define OS_INFO_BASE (0x80000300UL)
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#define OS_INFO ((os_info_t *) OS_INFO_BASE)
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#define OS_INFO_RESET_TYPE_COLD (0)
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#define OS_INFO_RESET_TYPE_NMI (1)
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uint32_t c0_count (void);
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void delay_ms (int ms);
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uint32_t cpu_io_read (io32_t *address);
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void cpu_io_write (io32_t *address, uint32_t value);
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void pi_io_config (uint8_t page_size, uint8_t latency, uint8_t pulse_width, uint8_t release);
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uint32_t pi_busy (void);
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uint32_t pi_io_read (io32_t *address);
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void pi_io_write (io32_t *address, uint32_t value);
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void pi_dma_read (io32_t *address, void *buffer, size_t length);
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void pi_dma_write (io32_t *address, void *buffer, size_t length);
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uint32_t si_busy (void);
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uint32_t si_io_read (io32_t *address);
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void si_io_write (io32_t *address, uint32_t value);
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void cache_data_hit_writeback_invalidate (void *address, size_t length);
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void cache_data_hit_writeback (void *address, size_t length);
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void cache_inst_hit_invalidate (void *address, size_t length);
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#endif
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