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https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-25 07:06:52 +01:00
108 lines
2.5 KiB
Verilog
108 lines
2.5 KiB
Verilog
module sd_clk (
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input i_clk,
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input i_reset,
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output reg o_sd_clk,
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input [1:0] i_sd_clk_config,
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output reg o_sd_clk_strobe_rising,
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output reg o_sd_clk_strobe_falling
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);
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// Clock configuration values
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localparam [1:0] SD_CLK_CONFIG_STOP = 2'd0;
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localparam [1:0] SD_CLK_CONFIG_DIV_256 = 2'd1;
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localparam [1:0] SD_CLK_CONFIG_DIV_4 = 2'd2;
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localparam [1:0] SD_CLK_CONFIG_DIV_2 = 2'd3;
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// Clock configuration change detection
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reg [1:0] r_prev_sd_clk_config;
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wire w_sd_clk_config_changed = r_prev_sd_clk_config != i_sd_clk_config;
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always @(posedge i_clk) begin
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if (i_reset) begin
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r_prev_sd_clk_config <= SD_CLK_CONFIG_STOP;
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end else begin
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r_prev_sd_clk_config <= i_sd_clk_config;
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end
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end
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// Clock divider
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reg [7:0] r_sd_clk_counter;
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always @(posedge i_clk) begin
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if (i_reset || w_sd_clk_config_changed) begin
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r_sd_clk_counter <= 8'd0;
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end else begin
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r_sd_clk_counter <= r_sd_clk_counter + 1'd1;
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end
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end
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// Clock divider selector
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reg r_selected_sd_clk;
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always @(*) begin
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case (r_prev_sd_clk_config)
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SD_CLK_CONFIG_STOP:
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r_selected_sd_clk = 1'b0;
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SD_CLK_CONFIG_DIV_256:
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r_selected_sd_clk = r_sd_clk_counter[7];
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SD_CLK_CONFIG_DIV_4:
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r_selected_sd_clk = r_sd_clk_counter[1];
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SD_CLK_CONFIG_DIV_2:
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r_selected_sd_clk = r_sd_clk_counter[0];
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endcase
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end
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// Clock strobe generation
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reg r_prev_selected_sd_clk;
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always @(posedge i_clk) begin
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o_sd_clk_strobe_rising <= 1'b0;
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o_sd_clk_strobe_falling <= 1'b0;
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if (i_reset) begin
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r_prev_selected_sd_clk <= 1'b0;
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end else begin
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r_prev_selected_sd_clk <= r_selected_sd_clk;
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if (!r_prev_selected_sd_clk && r_selected_sd_clk) begin
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o_sd_clk_strobe_rising <= 1'b1;
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end
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if (r_prev_selected_sd_clk && !r_selected_sd_clk) begin
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o_sd_clk_strobe_falling <= 1'b1;
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end
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end
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end
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// SD clock generation
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always @(posedge i_clk) begin
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if (i_reset) begin
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o_sd_clk <= 1'b0;
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end else begin
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if (o_sd_clk_strobe_rising) begin
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o_sd_clk <= 1'b1;
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end
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if (o_sd_clk_strobe_falling) begin
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o_sd_clk <= 1'b0;
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end
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end
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end
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endmodule
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