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https://github.com/Polprzewodnikowy/SummerCart64.git
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94 lines
2.2 KiB
Verilog
94 lines
2.2 KiB
Verilog
module sd_dma (
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input i_clk,
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input i_reset,
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input [3:0] i_dma_bank,
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input [23:0] i_dma_address,
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input [14:0] i_dma_length,
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output [14:0] o_dma_left,
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input i_dma_load_bank_address,
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input i_dma_load_length,
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input i_dma_direction,
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input i_dma_start,
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input i_dma_stop,
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output reg o_dma_busy,
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output o_rx_fifo_pop,
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input i_rx_fifo_empty,
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input [31:0] i_rx_fifo_data,
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output reg o_tx_fifo_push,
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input i_tx_fifo_full,
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output [31:0] o_tx_fifo_data,
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output o_request,
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output reg o_write,
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input i_busy,
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input i_ack,
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output reg [3:0] o_bank,
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output reg [23:0] o_address,
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input [31:0] i_data,
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output [31:0] o_data
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);
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wire w_request_successful = o_request && !i_busy;
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always @(posedge i_clk) begin
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if (i_dma_load_bank_address && !o_dma_busy) begin
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o_bank <= i_dma_bank;
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end
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end
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always @(posedge i_clk) begin
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if (i_dma_load_bank_address && !o_dma_busy) begin
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o_address <= i_dma_address;
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end else if (w_request_successful) begin
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o_address <= o_address + 1'd1;
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end
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end
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reg [14:0] r_remaining;
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assign o_dma_left = r_remaining;
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always @(posedge i_clk) begin
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if (i_dma_load_length && !o_dma_busy) begin
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r_remaining <= i_dma_length;
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end else if (w_request_successful && r_remaining > 15'd0) begin
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r_remaining <= r_remaining - 1'd1;
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end
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end
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always @(posedge i_clk) begin
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if (i_reset) begin
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o_dma_busy <= 1'b0;
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end else begin
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if (i_dma_start && !o_dma_busy) begin
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o_dma_busy <= 1'b1;
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end
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if (i_dma_stop || (w_request_successful && r_remaining == 15'd0)) begin
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o_dma_busy <= 1'b0;
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end
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end
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end
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assign o_rx_fifo_pop = o_dma_busy && o_write && w_request_successful;
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assign o_tx_fifo_data = i_data;
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assign o_request = o_dma_busy && (o_write ? (
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!i_rx_fifo_empty
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) : (
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1'b0 // TODO: Reading
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));
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always @(posedge i_clk) begin
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if (i_dma_start) begin
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o_write <= i_dma_direction;
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end
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end
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assign o_data = i_rx_fifo_data;
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endmodule
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