The-Homebrew-Cloud/SummerCart64
2
0
Fork 0
mirror of https://github.com/Polprzewodnikowy/SummerCart64.git synced 2024-11-25 15:16:53 +01:00
Code Issues Packages Projects Releases Wiki Activity
fe7b817d0e
SummerCart64/sw/riscv/src
History
Polprzewodnikowy 9bca165b4c escaping
2021-11-21 00:49:29 +01:00
..
cfg.c dum.py rewrite 2021-11-19 00:18:46 +01:00
cfg.h dum.py rewrite 2021-11-19 00:18:46 +01:00
dma.c [SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12) 2021-11-16 22:37:48 +01:00
dma.h [SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12) 2021-11-16 22:37:48 +01:00
flash.c [SC64][FW][SW] Load CPU software directly from embedded flash in FPGA (#9) 2021-10-26 23:44:09 +02:00
flash.h [SC64][FW][SW] Load CPU software directly from embedded flash in FPGA (#9) 2021-10-26 23:44:09 +02:00
flashram.c [SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12) 2021-11-16 22:37:48 +01:00
flashram.h [SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5) 2021-09-25 20:00:36 +02:00
i2c.c [SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5) 2021-09-25 20:00:36 +02:00
i2c.h [SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5) 2021-09-25 20:00:36 +02:00
joybus.c [SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5) 2021-09-25 20:00:36 +02:00
joybus.h [SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5) 2021-09-25 20:00:36 +02:00
process.c [SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12) 2021-11-16 22:37:48 +01:00
process.h [SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5) 2021-09-25 20:00:36 +02:00
rtc.c [SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12) 2021-11-16 22:37:48 +01:00
rtc.h [SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5) 2021-09-25 20:00:36 +02:00
startup.S [SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12) 2021-11-16 22:37:48 +01:00
sys.h escaping 2021-11-21 00:49:29 +01:00
uart.c [SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12) 2021-11-16 22:37:48 +01:00
uart.h [SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5) 2021-09-25 20:00:36 +02:00
usb.c escaping 2021-11-21 00:49:29 +01:00
usb.h [SC64][SW] Added USB debug feature (#8) 2021-10-23 21:55:52 +02:00