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52 lines
1.3 KiB
Verilog
52 lines
1.3 KiB
Verilog
module serv_bufreg #(
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parameter [0:0] MDU = 0
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)(
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input wire i_clk,
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//State
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input wire i_cnt0,
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input wire i_cnt1,
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input wire i_en,
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input wire i_init,
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input wire i_mdu_op,
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output wire [1:0] o_lsb,
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//Control
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input wire i_rs1_en,
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input wire i_imm_en,
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input wire i_clr_lsb,
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input wire i_sh_signed,
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//Data
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input wire i_rs1,
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input wire i_imm,
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output wire o_q,
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//External
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output wire [31:0] o_dbus_adr,
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//Extension
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output wire [31:0] o_ext_rs1);
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wire c, q;
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reg c_r;
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reg [31:2] data;
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reg [1:0] lsb;
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wire clr_lsb = i_cnt0 & i_clr_lsb;
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assign {c,q} = {1'b0,(i_rs1 & i_rs1_en)} + {1'b0,(i_imm & i_imm_en & !clr_lsb)} + c_r;
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always @(posedge i_clk) begin
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//Make sure carry is cleared before loading new data
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c_r <= c & i_en;
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if (i_en)
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data <= {i_init ? q : (data[31] & i_sh_signed), data[31:3]};
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if (i_init ? (i_cnt0 | i_cnt1) : i_en)
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lsb <= {i_init ? q : data[2],lsb[1]};
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end
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assign o_q = lsb[0] & i_en;
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assign o_dbus_adr = {data, 2'b00};
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assign o_ext_rs1 = {o_dbus_adr[31:2],lsb};
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assign o_lsb = (MDU & i_mdu_op) ? 2'b00 : lsb;
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endmodule
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