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70 lines
2.0 KiB
Verilog
70 lines
2.0 KiB
Verilog
`default_nettype none
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module serv_mem_if
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#(
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parameter [0:0] WITH_CSR = 1,
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parameter W = 1,
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parameter B = W-1
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)
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(
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input wire i_clk,
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//State
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input wire [1:0] i_bytecnt,
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input wire [1:0] i_lsb,
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output wire o_byte_valid,
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output wire o_misalign,
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//Control
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input wire i_signed,
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input wire i_word,
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input wire i_half,
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//MDU
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input wire i_mdu_op,
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//Data
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input wire [B:0] i_bufreg2_q,
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output wire [B:0] o_rd,
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//External interface
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output wire [3:0] o_wb_sel);
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reg signbit;
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/*
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Before a store operation, the data to be written needs to be shifted into
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place. Depending on the address alignment, we need to shift different
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amounts. One formula for calculating this is to say that we shift when
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i_lsb + i_bytecnt < 4. Unfortunately, the synthesis tools don't seem to be
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clever enough so the hideous expression below is used to achieve the same
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thing in a more optimal way.
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*/
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assign o_byte_valid
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= (!i_lsb[0] & !i_lsb[1]) |
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(!i_bytecnt[0] & !i_bytecnt[1]) |
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(!i_bytecnt[1] & !i_lsb[1]) |
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(!i_bytecnt[1] & !i_lsb[0]) |
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(!i_bytecnt[0] & !i_lsb[1]);
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wire dat_valid =
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i_mdu_op |
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i_word |
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(i_bytecnt == 2'b00) |
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(i_half & !i_bytecnt[1]);
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assign o_rd = dat_valid ? i_bufreg2_q : {W{i_signed & signbit}};
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assign o_wb_sel[3] = (i_lsb == 2'b11) | i_word | (i_half & i_lsb[1]);
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assign o_wb_sel[2] = (i_lsb == 2'b10) | i_word;
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assign o_wb_sel[1] = (i_lsb == 2'b01) | i_word | (i_half & !i_lsb[1]);
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assign o_wb_sel[0] = (i_lsb == 2'b00);
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always @(posedge i_clk) begin
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if (dat_valid)
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signbit <= i_bufreg2_q[B];
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end
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/*
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mem_misalign is checked after the init stage to decide whether to do a data
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bus transaction or go to the trap state. It is only guaranteed to be correct
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at this time
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*/
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assign o_misalign = WITH_CSR & ((i_lsb[0] & (i_word | i_half)) | (i_lsb[1] & i_word));
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endmodule
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