mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-29 08:44:15 +01:00
ff69030643
* isv support + usb/dd improvements
* make room for saves
* update offset
* fixed debug address
* idk
* exception
* ironed out all broken stuff
* cleanup
* return epc fix
* better
* more cleanup
* even more cleanup
* mooore cleanup
* fixed printf
* no assert
* improved docker build, pyft232 instead of pyserial
* fixed displaying long message strings
description test
* just straight cleanup
* smallest cleanup
* PAL
* cpu buffer
* n64 bootloader done
* super slow usb storage reading implemented
* reduced buffer size
* usb gets fast
* little cleanup
* double buffered reads
* removed separate event id
* ISV in hardware finally
* small exception changes
* mac testing
* py spacing
* fsd write, rtc, isv and reset fixes
* fixxx
* good stopping point
* usb fixed?
* pretend we have 128 MB sdram
* backup
* chmod
* test
* test done
* more tests
* user rm
* help
* final fix
* updated component values
* nice asset names
* cic 64dd support
* ddipl enable separation
* pre DMA rewrite, created dedicated buffer memory space, simplified code
* dma rewrite, needs testing
* moved xml
* dd basics
* timing
* 64dd working yet again, isv brought back, dma fixes, usb path rewrite, pc code rewrite
* added usb read functionality, general cleanup
* changed mem addressing
* added fpga flash update access
* added mcu update
* chmod
* little cleanup
* update format and stuff
* fixes
* uninitialized fix
* small fixes
* update fixes
* update stuff done
* fpga update tested
* build time fix
* boot fix
* test timing
* readme test
* test 2
* reports
* testseet
* final
* build test
* forgot
* button and naming
* General cleanup
And multiline commit message test
* Exception screen UI touch ups
* display separation and tests beginning
* pc software update
* pc software done
* timing test
* delete launch.json
* sw fixes
* fixed button hole diameter in shell
* small cleanup, rpi testing
* shell fillet fix, pc rtc printing
* added cfg lock mechanism
* moved lock to cfg address space
* extended ROM and ISV fixes
* preliminary sd card support
* little sd card cleanup
* sd menu fixes
* 5 second limit
* reduced shell thickness
* basic led act blinking
* faster sd menu loading
* inst cache invalidate
* sd card writing is working
* SD card CSD and CID registers
* wait for previous command
* led error codes
* fixed cfg_translate_address use
* 64dd from sd card working
* 64dd speedup and button handling
* delayed address latching cycle - might break other builds, needs testing
* bootloader improvements
* small fixes
* return previous cfg when setting new
* cache stuff
* unfloader debug protocol support
* UNFLoader style debug command line support
* requirements.txt
* shell groove fillet
* reset state inside controller
* fixed fast PI read, added PI R/W fifo debug info
* PI access prioritize
* SD clock stop when RX FIFO is more than half full
* flash erase method change
* CFG error handling, TLOZ MM debug ISV support
* CIC5167 support
* general fixes
* USB unplugged cable handling
* turn off led when changing between error/act modes
* rtc 2 bit clock stop support
* line endings
* Revert "line endings"
This reverts commit d0ddfe5ec7.
* PI address debug
* readme test
* diagram update
* diagram background
* diagram background
* diagram background
* updated readme
586 lines
18 KiB
C
586 lines
18 KiB
C
#include "button.h"
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#include "cfg.h"
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#include "dd.h"
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#include "flash.h"
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#include "fpga.h"
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#include "isv.h"
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#include "rtc.h"
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#include "sd.h"
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#include "usb.h"
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typedef enum {
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CFG_ID_BOOTLOADER_SWITCH,
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CFG_ID_ROM_WRITE_ENABLE,
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CFG_ID_ROM_SHADOW_ENABLE,
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CFG_ID_DD_MODE,
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CFG_ID_ISV_ADDRESS,
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CFG_ID_BOOT_MODE,
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CFG_ID_SAVE_TYPE,
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CFG_ID_CIC_SEED,
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CFG_ID_TV_TYPE,
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CFG_ID_DD_SD_ENABLE,
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CFG_ID_DD_DRIVE_TYPE,
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CFG_ID_DD_DISK_STATE,
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CFG_ID_BUTTON_STATE,
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CFG_ID_BUTTON_MODE,
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CFG_ID_ROM_EXTENDED_ENABLE,
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} cfg_id_t;
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typedef enum {
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DD_MODE_DISABLED = 0,
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DD_MODE_REGS = 1,
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DD_MODE_IPL = 2,
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DD_MODE_FULL = 3
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} dd_mode_t;
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typedef enum {
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BOOT_MODE_MENU = 0,
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BOOT_MODE_ROM = 1,
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BOOT_MODE_DD = 2,
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BOOT_MODE_DIRECT = 3
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} boot_mode_t;
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typedef enum {
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SAVE_TYPE_NONE = 0,
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SAVE_TYPE_EEPROM_4K = 1,
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SAVE_TYPE_EEPROM_16K = 2,
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SAVE_TYPE_SRAM = 3,
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SAVE_TYPE_FLASHRAM = 4,
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SAVE_TYPE_SRAM_BANKED = 5
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} save_type_t;
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typedef enum {
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CIC_SEED_UNKNOWN = 0xFFFF
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} cic_seed_t;
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typedef enum {
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TV_TYPE_PAL = 0,
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TV_TYPE_NTSC = 1,
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TV_TYPE_MPAL = 2,
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TV_TYPE_UNKNOWN = 3
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} tv_type_t;
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typedef enum {
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CFG_ERROR_OK = 0,
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CFG_ERROR_BAD_ARGUMENT = 1,
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CFG_ERROR_BAD_ADDRESS = 2,
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CFG_ERROR_BAD_CONFIG_ID = 3,
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CFG_ERROR_TIMEOUT = 4,
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CFG_ERROR_SD_CARD = 5,
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CFG_ERROR_UNKNOWN_CMD = -1,
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} cfg_error_t;
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typedef enum {
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SD_CARD_OP_DEINIT = 0,
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SD_CARD_OP_INIT = 1,
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SD_CARD_OP_GET_STATUS = 2,
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SD_CARD_OP_GET_INFO = 3,
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} sd_card_op_t;
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typedef enum {
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SDRAM = (1 << 0),
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FLASH = (1 << 1),
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BRAM = (1 << 2),
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} translate_type_t;
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struct process {
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boot_mode_t boot_mode;
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save_type_t save_type;
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cic_seed_t cic_seed;
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tv_type_t tv_type;
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bool usb_output_ready;
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uint32_t sd_card_sector;
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};
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static struct process p;
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static void cfg_set_usb_output_ready (void) {
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p.usb_output_ready = true;
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}
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static bool cfg_translate_address (uint32_t *address, uint32_t length, translate_type_t type) {
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if (length == 0) {
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return true;
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}
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*address &= 0x1FFFFFFF;
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if (type & SDRAM) {
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if (*address >= 0x06000000 && *address < 0x06400000) {
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if ((*address + length) <= 0x06400000) {
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*address = *address - 0x06000000 + 0x03BC0000;
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return false;
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}
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}
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if (*address >= 0x08000000 && *address < 0x08020000) {
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if ((*address + length) <= 0x08020000) {
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*address = *address - 0x08000000 + 0x03FE0000;
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return false;
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}
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}
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if (*address >= 0x10000000 && *address < 0x14000000) {
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if ((*address + length) <= 0x14000000) {
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*address = *address - 0x10000000 + 0x00000000;
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return false;
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}
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}
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}
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if (type & FLASH) {
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if (*address >= 0x14000000 && *address < 0x14E00000) {
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if ((*address + length) <= 0x14E00000) {
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*address = *address - 0x14000000 + 0x04000000;
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return false;
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}
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}
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if (*address >= 0x1FFC0000 && *address < 0x1FFE0000) {
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if ((*address + length) <= 0x1FFE0000) {
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*address = *address - 0x1FFC0000 + 0x04E00000;
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return false;
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}
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}
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}
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if (type & BRAM) {
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if (*address >= 0x1FFE0000 && *address < 0x1FFE2000) {
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if ((*address + length) <= 0x1FFE2000) {
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*address = *address - 0x1FFE0000 + 0x05000000;
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return false;
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}
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}
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if (*address >= 0x1FFE2000 && *address < 0x1FFE2800) {
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if ((*address + length) <= 0x1FFE2800) {
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*address = *address - 0x1FFE2000 + 0x05002000;
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return false;
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}
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}
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}
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return true;
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}
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static void cfg_set_error (cfg_error_t error) {
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fpga_reg_set(REG_CFG_DATA_0, error);
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fpga_reg_set(REG_CFG_DATA_1, 0);
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fpga_reg_set(REG_CFG_CMD, CFG_CMD_ERROR | CFG_CMD_DONE);
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}
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static void cfg_change_scr_bits (uint32_t mask, bool value) {
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if (value) {
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fpga_reg_set(REG_CFG_SCR, fpga_reg_get(REG_CFG_SCR) | mask);
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} else {
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fpga_reg_set(REG_CFG_SCR, fpga_reg_get(REG_CFG_SCR) & (~mask));
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}
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}
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static bool cfg_set_save_type (save_type_t save_type) {
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if (save_type > SAVE_TYPE_SRAM_BANKED) {
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return true;
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}
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uint32_t save_reset_mask = (
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CFG_SCR_EEPROM_16K |
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CFG_SCR_EEPROM_ENABLED |
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CFG_SCR_FLASHRAM_ENABLED |
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CFG_SCR_SRAM_BANKED |
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CFG_SCR_SRAM_ENABLED
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);
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cfg_change_scr_bits(save_reset_mask, false);
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switch (save_type) {
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case SAVE_TYPE_NONE:
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break;
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case SAVE_TYPE_EEPROM_4K:
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cfg_change_scr_bits(CFG_SCR_EEPROM_ENABLED, true);
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break;
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case SAVE_TYPE_EEPROM_16K:
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cfg_change_scr_bits(CFG_SCR_EEPROM_16K | CFG_SCR_EEPROM_ENABLED, true);
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break;
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case SAVE_TYPE_SRAM:
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cfg_change_scr_bits(CFG_SCR_SRAM_ENABLED, true);
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break;
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case SAVE_TYPE_FLASHRAM:
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cfg_change_scr_bits(CFG_SCR_FLASHRAM_ENABLED, true);
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break;
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case SAVE_TYPE_SRAM_BANKED:
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cfg_change_scr_bits(CFG_SCR_SRAM_BANKED | CFG_SCR_SRAM_ENABLED, true);
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break;
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default:
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save_type = SAVE_TYPE_NONE;
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break;
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}
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p.save_type = save_type;
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return false;
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}
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uint32_t cfg_get_version (void) {
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return fpga_reg_get(REG_CFG_VERSION);
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}
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bool cfg_query (uint32_t *args) {
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uint32_t scr = fpga_reg_get(REG_CFG_SCR);
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switch (args[0]) {
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case CFG_ID_BOOTLOADER_SWITCH:
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args[1] = (scr & CFG_SCR_BOOTLOADER_ENABLED);
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break;
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case CFG_ID_ROM_WRITE_ENABLE:
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args[1] = (scr & CFG_SCR_ROM_WRITE_ENABLED);
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break;
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case CFG_ID_ROM_SHADOW_ENABLE:
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args[1] = (scr & CFG_SCR_ROM_SHADOW_ENABLED);
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break;
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case CFG_ID_DD_MODE:
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args[1] = DD_MODE_DISABLED;
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if (scr & CFG_SCR_DDIPL_ENABLED) {
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args[1] |= DD_MODE_IPL;
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}
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if (scr & CFG_SCR_DD_ENABLED) {
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args[1] |= DD_MODE_REGS;
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}
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break;
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case CFG_ID_ISV_ADDRESS:
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args[1] = isv_get_address();
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break;
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case CFG_ID_BOOT_MODE:
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args[1] = p.boot_mode;
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break;
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case CFG_ID_SAVE_TYPE:
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args[1] = p.save_type;
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break;
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case CFG_ID_CIC_SEED:
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args[1] = p.cic_seed;
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break;
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case CFG_ID_TV_TYPE:
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args[1] = p.tv_type;
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break;
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case CFG_ID_DD_SD_ENABLE:
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args[1] = dd_get_sd_mode();
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break;
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case CFG_ID_DD_DRIVE_TYPE:
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args[1] = dd_get_drive_type();
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break;
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case CFG_ID_DD_DISK_STATE:
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args[1] = dd_get_disk_state();
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break;
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case CFG_ID_BUTTON_STATE:
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args[1] = button_get_state();
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break;
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case CFG_ID_BUTTON_MODE:
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args[1] = button_get_mode();
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break;
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case CFG_ID_ROM_EXTENDED_ENABLE:
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args[1] = (scr & CFG_SCR_ROM_EXTENDED_ENABLED);
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break;
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default:
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return true;
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}
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return false;
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}
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bool cfg_update (uint32_t *args) {
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switch (args[0]) {
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case CFG_ID_BOOTLOADER_SWITCH:
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cfg_change_scr_bits(CFG_SCR_BOOTLOADER_ENABLED, args[1]);
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break;
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case CFG_ID_ROM_WRITE_ENABLE:
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cfg_change_scr_bits(CFG_SCR_ROM_WRITE_ENABLED, args[1]);
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break;
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case CFG_ID_ROM_SHADOW_ENABLE:
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cfg_change_scr_bits(CFG_SCR_ROM_SHADOW_ENABLED, args[1]);
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break;
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case CFG_ID_DD_MODE:
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if (args[1] == DD_MODE_DISABLED) {
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cfg_change_scr_bits(CFG_SCR_DD_ENABLED | CFG_SCR_DDIPL_ENABLED, false);
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} else if (args[1] == DD_MODE_REGS) {
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cfg_change_scr_bits(CFG_SCR_DD_ENABLED, true);
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cfg_change_scr_bits(CFG_SCR_DDIPL_ENABLED, false);
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} else if (args[1] == DD_MODE_IPL) {
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cfg_change_scr_bits(CFG_SCR_DD_ENABLED, false);
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cfg_change_scr_bits(CFG_SCR_DDIPL_ENABLED, true);
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} else if (args[1] == DD_MODE_FULL) {
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cfg_change_scr_bits(CFG_SCR_DD_ENABLED | CFG_SCR_DDIPL_ENABLED, true);
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} else {
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return true;
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}
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break;
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case CFG_ID_ISV_ADDRESS:
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return isv_set_address(args[1]);
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break;
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case CFG_ID_BOOT_MODE:
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if (args[1] > BOOT_MODE_DIRECT) {
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return true;
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}
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p.boot_mode = args[1];
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cfg_change_scr_bits(CFG_SCR_BOOTLOADER_SKIP, (args[1] == BOOT_MODE_DIRECT));
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break;
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case CFG_ID_SAVE_TYPE:
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return cfg_set_save_type((save_type_t) (args[1]));
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break;
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case CFG_ID_CIC_SEED:
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if ((args[1] != 0xFFFF) && (args[1] > 0x1FF)) {
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return true;
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}
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p.cic_seed = (cic_seed_t) (args[1] & 0xFFFF);
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break;
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case CFG_ID_TV_TYPE:
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if (args[1] > TV_TYPE_UNKNOWN) {
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return true;
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}
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p.tv_type = (tv_type_t) (args[1] & 0x03);
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break;
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case CFG_ID_DD_SD_ENABLE:
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dd_set_sd_mode(args[1]);
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break;
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case CFG_ID_DD_DRIVE_TYPE:
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return dd_set_drive_type(args[1]);
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break;
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case CFG_ID_DD_DISK_STATE:
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return dd_set_disk_state(args[1]);
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break;
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case CFG_ID_BUTTON_STATE:
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return true;
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break;
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case CFG_ID_BUTTON_MODE:
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return button_set_mode(args[1]);
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break;
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case CFG_ID_ROM_EXTENDED_ENABLE:
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cfg_change_scr_bits(CFG_SCR_ROM_EXTENDED_ENABLED, args[1]);
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break;
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default:
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return true;
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}
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return false;
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}
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void cfg_get_time (uint32_t *args) {
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rtc_time_t t;
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rtc_get_time(&t);
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args[0] = ((t.hour << 16) | (t.minute << 8) | t.second);
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args[1] = ((t.weekday << 24) | (t.year << 16) | (t.month << 8) | t.day);
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}
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void cfg_set_time (uint32_t *args) {
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rtc_time_t t;
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t.second = (args[0] & 0xFF);
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t.minute = ((args[0] >> 8) & 0xFF);
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t.hour = ((args[0] >> 16) & 0xFF);
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t.weekday = ((args[0] >> 24) & 0xFF);
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t.day = (args[1] & 0xFF);
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t.month = ((args[1] >> 8) & 0xFF);
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t.year = ((args[1] >> 16) & 0xFF);
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rtc_set_time(&t);
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}
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void cfg_reset_state (void) {
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uint32_t mask = (
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CFG_SCR_BOOTLOADER_SKIP |
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CFG_SCR_ROM_WRITE_ENABLED |
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CFG_SCR_ROM_SHADOW_ENABLED |
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CFG_SCR_DD_ENABLED |
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CFG_SCR_DDIPL_ENABLED |
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CFG_SCR_ROM_EXTENDED_ENABLED
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);
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cfg_change_scr_bits(mask, false);
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cfg_set_save_type(SAVE_TYPE_NONE);
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button_set_mode(BUTTON_MODE_NONE);
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dd_set_drive_type(DD_DRIVE_TYPE_RETAIL);
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dd_set_disk_state(DD_DISK_STATE_EJECTED);
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dd_set_sd_mode(false);
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isv_set_address(0);
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p.cic_seed = CIC_SEED_UNKNOWN;
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p.tv_type = TV_TYPE_UNKNOWN;
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p.boot_mode = BOOT_MODE_MENU;
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}
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void cfg_init (void) {
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fpga_reg_set(REG_CFG_SCR, CFG_SCR_BOOTLOADER_ENABLED);
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cfg_reset_state();
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p.usb_output_ready = true;
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}
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void cfg_process (void) {
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uint32_t reg;
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uint32_t args[2];
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uint32_t prev_cfg[2];
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usb_tx_info_t packet_info;
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reg = fpga_reg_get(REG_CFG_CMD);
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if (reg & CFG_CMD_PENDING) {
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args[0] = fpga_reg_get(REG_CFG_DATA_0);
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args[1] = fpga_reg_get(REG_CFG_DATA_1);
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char cmd = (char) ((reg & CFG_CMD_MASK) >> CFG_CMD_BIT);
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switch (cmd) {
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case 'v':
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args[0] = cfg_get_version();
|
|
break;
|
|
|
|
case 'c':
|
|
if (cfg_query(args)) {
|
|
cfg_set_error(CFG_ERROR_BAD_CONFIG_ID);
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case 'C':
|
|
prev_cfg[0] = args[0];
|
|
cfg_query(prev_cfg);
|
|
if (cfg_update(args)) {
|
|
cfg_set_error(CFG_ERROR_BAD_CONFIG_ID);
|
|
return;
|
|
}
|
|
args[1] = prev_cfg[1];
|
|
break;
|
|
|
|
case 't':
|
|
cfg_get_time(args);
|
|
break;
|
|
|
|
case 'T':
|
|
cfg_set_time(args);
|
|
break;
|
|
|
|
case 'm':
|
|
if (cfg_translate_address(&args[0], args[1], (SDRAM | BRAM))) {
|
|
cfg_set_error(CFG_ERROR_BAD_ADDRESS);
|
|
return;
|
|
}
|
|
if (!usb_prepare_read(args)) {
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case 'M':
|
|
if (cfg_translate_address(&args[0], args[1] & 0xFFFFFF, (SDRAM | BRAM))) {
|
|
cfg_set_error(CFG_ERROR_BAD_ADDRESS);
|
|
return;
|
|
}
|
|
usb_create_packet(&packet_info, PACKET_CMD_DEBUG_OUTPUT);
|
|
packet_info.data_length = 4;
|
|
packet_info.data[0] = args[1];
|
|
packet_info.dma_length = (args[1] & 0xFFFFFF);
|
|
packet_info.dma_address = args[0];
|
|
packet_info.done_callback = cfg_set_usb_output_ready;
|
|
if (usb_enqueue_packet(&packet_info)) {
|
|
p.usb_output_ready = false;
|
|
} else {
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case 'u':
|
|
usb_get_read_info(args);
|
|
break;
|
|
|
|
case 'U':
|
|
args[0] = p.usb_output_ready ? 0 : (1 << 31);
|
|
break;
|
|
|
|
case 'i':
|
|
switch (args[1]) {
|
|
case SD_CARD_OP_DEINIT:
|
|
sd_card_deinit();
|
|
break;
|
|
case SD_CARD_OP_INIT:
|
|
if (sd_card_init()) {
|
|
cfg_set_error(CFG_ERROR_SD_CARD);
|
|
return;
|
|
}
|
|
break;
|
|
case SD_CARD_OP_GET_STATUS:
|
|
args[1] = sd_card_get_status();
|
|
break;
|
|
case SD_CARD_OP_GET_INFO:
|
|
if (cfg_translate_address(&args[0], 32, (SDRAM | BRAM))) {
|
|
cfg_set_error(CFG_ERROR_BAD_ADDRESS);
|
|
return;
|
|
}
|
|
if (sd_card_get_info(args[0])) {
|
|
cfg_set_error(CFG_ERROR_SD_CARD);
|
|
return;
|
|
}
|
|
break;
|
|
default:
|
|
cfg_set_error(CFG_ERROR_BAD_ARGUMENT);
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case 'I':
|
|
p.sd_card_sector = args[0];
|
|
break;
|
|
|
|
case 's':
|
|
if (args[1] >= 0x800000) {
|
|
cfg_set_error(CFG_ERROR_BAD_ARGUMENT);
|
|
return;
|
|
}
|
|
if (cfg_translate_address(&args[0], args[1] * SD_SECTOR_SIZE, (SDRAM | BRAM | FLASH))) {
|
|
cfg_set_error(CFG_ERROR_BAD_ADDRESS);
|
|
return;
|
|
}
|
|
if (sd_read_sectors(args[0], p.sd_card_sector, args[1])) {
|
|
cfg_set_error(CFG_ERROR_SD_CARD);
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case 'S':
|
|
if (args[1] >= 0x800000) {
|
|
cfg_set_error(CFG_ERROR_BAD_ARGUMENT);
|
|
return;
|
|
}
|
|
if (cfg_translate_address(&args[0], args[1] * SD_SECTOR_SIZE, (SDRAM | BRAM | FLASH))) {
|
|
cfg_set_error(CFG_ERROR_BAD_ADDRESS);
|
|
return;
|
|
}
|
|
if (sd_write_sectors(args[0], p.sd_card_sector, args[1])) {
|
|
cfg_set_error(CFG_ERROR_SD_CARD);
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case 'D':
|
|
if (cfg_translate_address(&args[0], args[1], (SDRAM | BRAM))) {
|
|
cfg_set_error(CFG_ERROR_BAD_ADDRESS);
|
|
return;
|
|
}
|
|
dd_set_sd_disk_info(args[0], args[1]);
|
|
break;
|
|
|
|
case 'p':
|
|
flash_wait_busy();
|
|
args[0] = FLASH_ERASE_BLOCK_SIZE;
|
|
break;
|
|
|
|
case 'P':
|
|
if (cfg_translate_address(&args[0], FLASH_ERASE_BLOCK_SIZE, FLASH)) {
|
|
cfg_set_error(CFG_ERROR_BAD_ADDRESS);
|
|
return;
|
|
}
|
|
flash_erase_block(args[0]);
|
|
break;
|
|
|
|
case '?':
|
|
args[0] = fpga_reg_get(REG_DEBUG_0);
|
|
args[1] = fpga_reg_get(REG_DEBUG_1);
|
|
break;
|
|
|
|
default:
|
|
cfg_set_error(CFG_ERROR_UNKNOWN_CMD);
|
|
return;
|
|
}
|
|
|
|
fpga_reg_set(REG_CFG_DATA_0, args[0]);
|
|
fpga_reg_set(REG_CFG_DATA_1, args[1]);
|
|
fpga_reg_set(REG_CFG_CMD, CFG_CMD_DONE);
|
|
}
|
|
}
|