mirror of
https://github.com/Fledge68/WiiFlow_Lite.git
synced 2024-11-01 09:05:06 +01:00
193 lines
2.9 KiB
ArmAsm
193 lines
2.9 KiB
ArmAsm
.set r0,0; .set r1,1; .set r2,2; .set r3,3; .set r4,4;
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.set r5,5; .set r6,6; .set r7,7; .set r8,8; .set r9,9;
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.set r10,10; .set r11,11; .set r12,12; .set r13,13; .set r14,14;
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.set r15,15; .set r16,16; .set r17,17; .set r18,18; .set r19,19;
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.set r20,20; .set r21,21; .set r22,22; .set r23,23; .set r24,24;
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.set r25,25; .set r26,26; .set r27,27; .set r28,28; .set r29,29;
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.set r30,30; .set r31,31;
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#include "hw.h"
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.global __temp_abe
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__temp_abe:
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mfspr r3,rHID0
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ori r4,r3,HID0_ABE #HID0[ABE]
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mtspr rHID0,r4
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isync
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sync
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mtspr rHID0,r3
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rfi
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.global DCFlashInvalidate
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DCFlashInvalidate:
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nop
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mfspr r3,rHID0
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ori r3,r3,HID0_DCFI #HID0[DCFI]
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mtspr rHID0,r3
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blr
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.global DCacheEnable
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DCacheEnable:
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sync
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mfspr r3,rHID0
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ori r3,r3,HID0_DCE #HID0[DCE]
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mtspr rHID0,r3
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blr
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.global DCBlockInvalidate
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DCBlockInvalidate:
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cmplwi r4,0
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blelr
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clrlwi. r5,r3,27
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beq- 0f
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addi r4,r4,0x20
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0:
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addi r4,r4,0x1F
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rlwinm r4,r4,27,5,31
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mtctr r4
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1:
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dcbi r0,r3
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addi r3,r3,0x20
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bdnz+ 1b
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blr
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DCBlockFlushSc:
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cmplwi r4,0
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blelr
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clrlwi. r5,r3,27
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beq- 0f
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addi r4,r4,0x20
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0:
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addi r4,r4,0x1F
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rlwinm r4,r4,27,5,31
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mtctr r4
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1:
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dcbf r0,r3
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addi r3,r3,0x20
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bdnz+ 1b
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sc
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blr
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DCBlockFlush:
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cmplwi r4,0
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blelr
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clrlwi. r5,r3,27
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beq- 0f
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addi r4,r4,0x20
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0:
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addi r4,r4,0x1F
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rlwinm r4,r4,27,5,31
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mtctr r4
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1:
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dcbf r0,r3
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addi r3,r3,0x20
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bdnz+ 1b
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blr
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.global ICInvalidateRange
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ICInvalidateRange:
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cmplwi r4,0
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blelr
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clrlwi. r5,r3,27
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beq- 0f
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addi r4,r4,0x20
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0:
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addi r4,r4,0x1F
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rlwinm r4,r4,27,5,31
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mtctr r4
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1:
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icbi r0,r3
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addi r3,r3,0x20
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bdnz+ 1b
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sync
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isync
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blr
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ICFlashInvalidate:
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mfspr r3,rHID0
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ori r3,r3,HID0_ICFI #HID0[ICFI]
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mtspr rHID0,r3
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blr
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.global ICacheEnable
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ICacheEnable:
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isync
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mfspr r3,rHID0
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ori r3,r3,HID0_ICE #HID0[ICE]
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mtspr rHID0,r3
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blr
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ICacheDisable:
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isync
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mfspr r3,rHID0
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rlwinm r3,r3,0,17,15 #HID0[ICE]
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mtspr rHID0,r3
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blr
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ISync:
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isync
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blr
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.global L2_Init
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L2_Init:
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mflr r0
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stw r0, 0x04(r1)
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stwu r1,-0x10(r1)
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stw r31,0x0C(r1)
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mfmsr r3
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mr r31,r3
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sync
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li r3,MSR_IR|MSR_DR #MSR[IR|DR]
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mtmsr r3
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sync
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bl L2_Disable
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bl L2_Invalidate
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mr r3,r31
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mtmsr r3
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lwz r0, 0x14(r1)
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lwz r31,0x0C(r1)
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mtlr r0
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blr
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.global L2_Enable
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L2_Enable:
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mfl2cr r3
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oris r0,r3,0x8000 #L2CR[L2E]
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rlwinm r3,r0,0,11,9 #L2CR[L2I]
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mtl2cr r3
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blr
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L2_Disable:
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sync
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mfl2cr r3
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clrlwi r3,r3,1 #L2CR[L2E]
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mtl2cr r3
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sync
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blr
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L2_Invalidate:
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mflr r0
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stw r0, 0x04(r1)
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stwu r1,-0x08(r1)
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bl L2_Disable
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mfl2cr r3
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oris r3,r3,0x200 #L2CR[L2I]
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mtl2cr r3
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0:
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mfl2cr r3
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clrlwi r0,r3,31 #L2CR[L2IP]
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cmplwi r0,0
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bne+ 0b
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mfl2cr r3
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rlwinm r3,r3,0,11,9 #L2CR[L2I]
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mtl2cr r3
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1:
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mfl2cr r3
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clrlwi r0,r3,31 #L2CR[L2IP]
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cmplwi r0,0
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bne+ 1b
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lwz r0,0x0C(r1)
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addi r1,r1,0x08
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mtlr r0
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blr
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