mirror of
https://github.com/Fledge68/WiiFlow_Lite.git
synced 2024-11-01 09:05:06 +01:00
257 lines
4.6 KiB
ArmAsm
257 lines
4.6 KiB
ArmAsm
# Copyright 2008-2009 Segher Boessenkool <segher@kernel.crashing.org>
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# This code is licensed to you under the terms of the GNU GPL, version 2;
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# see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
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.set r0,0; .set r1,1; .set r2,2; .set r3,3; .set r4,4;
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.set r5,5; .set r6,6; .set r7,7; .set r8,8; .set r9,9;
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.set r10,10; .set r11,11; .set r12,12; .set r13,13; .set r14,14;
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.set r15,15; .set r16,16; .set r17,17; .set r18,18; .set r19,19;
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.set r20,20; .set r21,21; .set r22,22; .set r23,23; .set r24,24;
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.set r25,25; .set r26,26; .set r27,27; .set r28,28; .set r29,29;
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.set r30,30; .set r31,31;
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#include "hw.h"
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.globl _start
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_start:
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mfmsr r3
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rlwinm r4,r3,0,17,15 # MSR_EE
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rlwinm r4,r4,0,26,24 # MSR_IP
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mtmsr r4
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isync
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lis r3,_setup@h
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ori r3,r3,_setup@l
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clrlwi r3,r3,2
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mtsrr0 r3
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mfmsr r3
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li r4,MSR_IR|MSR_DR
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andc r3,r3,r4
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mtsrr1 r3
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rfi
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#0001 0001 0000 1100 0110 0100
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#BHT,BTIC,DCFA,DCFI,ICFI,NHR,DPM
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_setup:
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lis r3,0x11
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ori r3,r3,0xC64 #0x110C64
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mtspr rHID0,r3
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isync
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li r4,MSR_FP
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mtmsr r4
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ori r3,r3,HID0_ICE|HID0_DCE
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mtspr rHID0,r3
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isync
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li r0,0
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mtibatu 0,r0
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mtibatu 1,r0
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mtibatu 2,r0
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mtibatu 3,r0
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mtdbatu 0,r0
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mtdbatu 1,r0
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mtdbatu 2,r0
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mtdbatu 3,r0
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#mtibatl 0,r0
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mtspr 560,r0
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mtspr 562,r0
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mtspr 564,r0
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mtspr 566,r0
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mtspr 568,r0
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mtspr 570,r0
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mtspr 572,r0
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mtspr 574,r0
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isync
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lis r0,0x8000
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mtsr 0,r0
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mtsr 1,r0
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mtsr 2,r0
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mtsr 3,r0
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mtsr 4,r0
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mtsr 5,r0
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mtsr 6,r0
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mtsr 7,r0
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mtsr 8,r0
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mtsr 9,r0
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mtsr 10,r0
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mtsr 11,r0
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mtsr 12,r0
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mtsr 13,r0
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mtsr 14,r0
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mtsr 15,r0
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isync
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li r3,2 #0x00000000|PP=2
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lis r4,0x8000
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ori r4,r4,0x1FFF #0x80000000|256Mbytes|VS|VP
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mtibatl 0,r3
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mtibatu 0,r4
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mtdbatl 0,r3
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mtdbatu 0,r4
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isync
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addis r3,r3,0x1000 #0x10000000|PP=2
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addis r4,r4,0x1000 #0x90000000|256Mbytes|VS|VP
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mtspr 561,r3
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mtspr 560,r4
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mtspr 569,r3
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mtspr 568,r4
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isync
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li r3,0x2A #0x00000000|I|G|PP=2
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lis r4,0xC000
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ori r4,r4,0x1FFF #0xC0000000|256Mbytes|VS|VP
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mtdbatu 1,r3
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mtdbatu 1,r4
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isync
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addis r3,r3,0x1000 #0x10000000|I|G|PP=2
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addis r4,r4,0x1000 #0xD0000000|256Mbytes|VS|VP
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mtspr 571,r3
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mtspr 570,r4
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isync
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lis r3,0x8200
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mtspr 1011,r3
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lis r3,_init@h
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ori r3,r3,_init@l
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mtsrr0 r3
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mfmsr r3
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ori r3,r3,MSR_DR|MSR_IR
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mtsrr1 r3
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rfi
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.extern _main
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#TODO - fixup memset
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_init:
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bl __init_registers
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bl __init_memory
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bl __init_syscall
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bl __init_sprs
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lis r3,__bss_start@h
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ori r3,r3,__bss_start@l
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li r4,0
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lis r5,__bss_end@h
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ori r5,r5,__bss_end@l
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subf r5,r3,r5
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bl _memset
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lis r3,__stack_end@h
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ori r3,r3,__stack_end@l
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li r4,0
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lis r5,__stack_top@h
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ori r5,r5,__stack_top@l
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subf r5,r3,r5
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bl _memset
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bl _main
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0:
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b 0b
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__init_registers:
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li r0,0
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li r3,0
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li r4,0
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li r5,0
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li r6,0
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li r7,0
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li r8,0
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li r9,0
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li r10,0
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li r11,0
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li r12,0
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li r14,0
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li r15,0
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li r16,0
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li r17,0
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li r18,0
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li r19,0
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li r20,0
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li r21,0
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li r22,0
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li r23,0
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li r24,0
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li r25,0
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li r26,0
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li r27,0
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li r28,0
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li r29,0
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li r30,0
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li r31,0
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lis r1,__stack_top@h
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ori r1,r1,__stack_top@l
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addi r1,r1,-4
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stw r0,0(r1)
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stwu r1,-0x38(r1)
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lis r2,0
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ori r2,r2,0x8000
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lis r13,0
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ori r13,r13,0x8000
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blr
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_memset:
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clrlwi. r6,r5,29
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rlwinm r5,r5,30,2,31
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addi r3,r3,-4
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mtctr r5
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0:
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stwu r4,4(r3)
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bdnz+ 0b
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cmplwi r6,0
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beq- 2f
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1:
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stbu r4,1(r3)
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addic. r6,r6,-1
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bne+ 1b
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2:
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blr
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__init_memory:
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mflr r0
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stw r0, 0x04(r1)
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stwu r1,-0x10(r1)
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stw r31,0x0C(r1)
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mfspr r3,rHID0
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rlwinm r0,r3,0,16,16 #HID0[ICE]
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cmplwi r0,0
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bne- 0f
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bl ICacheEnable
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0:
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mfspr r3,rHID0
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rlwinm r0,r3,0,17,17 #HID0[DCE]
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cmplwi r0,0
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bne- 1f
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bl DCacheEnable
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1:
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mfl2cr r3
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rlwinm r0,r3,0,0,0 #L2CR[L2E]
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cmplwi r0,0
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bne- 2f
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bl L2_Init
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bl L2_Enable
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2:
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lwz r0, 0x14(r1)
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lwz r31,0x0C(r1)
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addi r1,r1,0x10
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mtlr r0
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blr
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__init_sprs:
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mflr r0
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stw r0, 0x04(r1)
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stwu r1,-0x18(r1)
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stw r31,0x14(r1)
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stw r30,0x10(r1)
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stw r29,0x0C(r1)
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li r3,0
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mtmmcr0 r3
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mtmmcr1 r3
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mtpmc1 r3
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mtpmc2 r3
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mtpmc3 r3
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mtpmc4 r3
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mfspr r3,rHID0
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ori r3,r3,HID0_SPD #HID0[SPD]
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mtspr rHID0,r3
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mfspr r3,rHID2
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rlwinm r3,r3,0,2,0 #HID2[WPE]
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mtspr rHID2,r3
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lwz r0, 0x1C(r1)
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lwz r31,0x14(r1)
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lwz r30,0x10(r1)
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lwz r29,0x0C(r1)
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addi r1,r1,0x18
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mtlr r0
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blr
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