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410 lines
13 KiB
C
410 lines
13 KiB
C
/* caam_driver.h
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*
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* Copyright (C) 2006-2021 wolfSSL Inc.
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*
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* This file is part of wolfSSL.
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*
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* wolfSSL is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfSSL is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef CAAM_DRIVER_H
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#define CAAM_DRIVER_H
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#if (defined(__QNX__) || defined(__QNXNTO__))
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int InitCAAM(void);
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#include "caam_qnx.h"
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#endif
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#if (defined(__INTEGRITY) || defined(INTEGRITY))
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#define CAAM_BASE 0xf2100000
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#define CAAM_PAGE 0xf0100000
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#endif
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#define CAAM_PAGE_MAX 6
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/* max size of 64 word32's */
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#define CAAM_DESC_MAX 256
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#ifndef CAAM_JOBRING_SIZE
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#define CAAM_JOBRING_SIZE 1
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#endif
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/******************************************************************************
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Basic Descriptors
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****************************************************************************/
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/* descriptor commands */
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#define CAAM_KEY 0x00000000
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#define CAAM_LOAD 0x10000000
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#define CAAM_LOAD_CTX 0x10200000
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#define CAAM_IMM 0x00800000
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#define CAAM_FIFO_L 0x20000000
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#define CAAM_FIFO_S 0x60000000
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#define CAAM_FIFO_S_SKEY 0x60260000
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#define CAAM_STORE 0x50000000
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#define CAAM_STORE_CTX 0x50200000
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#define CAAM_MOVE 0x78000000
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#define CAAM_OP 0x80000000
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#define CAAM_SIG 0x90000000
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#define CAAM_JUMP 0xA0000000
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#define CAAM_SEQI 0xF0000000/* SEQ in */
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#define CAAM_SEQO 0xF8000000/* SEQ out */
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#define CAAM_HEAD 0xB0800000
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#define CAAM_NWB 0x00200000
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/* PROTOCOL OPERATION command */
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#define CAAM_PROT_UNIDI 0
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#define CAAM_BLOB_ENCAP 0x07000000
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#define CAAM_BLOB_DECAP 0x06000000
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#define CAAM_PKHA_OP 0x01000000
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#define CAAM_OPID_BLOB 0x000D0000
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/* algorithms modes and types */
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#define CAAM_CLASS1 0x02000000/* i.e. AES, PKHA */
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#define CAAM_CLASS2 0x04000000/* i.e. hash algos */
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#define CAAM_ENC 0x00000001
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#define CAAM_DEC 0x00000000
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#define CAAM_ALG_INIT 0x00000004
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#define CAAM_ALG_INITF 0x0000000C
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#define CAAM_ALG_UPDATE 0x00000000
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#define CAAM_ALG_FINAL 0x00000008
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/* AES 10h */
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#define CAAM_AESCTR 0x00100000
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#define CAAM_AESCBC 0x00100100
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#define CAAM_AESECB 0x00100200
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#define CAAM_AESCFB 0x00100300
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#define CAAM_AESOFB 0x00100400
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#define CAAM_CMAC 0x00100600
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#define CAAM_AESCCM 0x00100800
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/* HASH 40h */
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#define CAAM_MD5 0x00400000
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#define CAAM_SHA 0x00410000
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#define CAAM_SHA224 0x00420000
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#define CAAM_SHA256 0x00430000
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#define CAAM_SHA384 0x00440000
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#define CAAM_SHA512 0x00450000
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/* HMAC 40h + 10 AAI */
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#define CAAM_HMAC_MD5 0x00400010
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#define CAAM_HMAC_SHA 0x00410010
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#define CAAM_HMAC_SHA224 0x00420010
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#define CAAM_HMAC_SHA256 0x00430010
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#define CAAM_HMAC_SHA384 0x00440010
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#define CAAM_HMAC_SHA512 0x00450010
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/* ECDSA ECDSEL (pre defined flags for ECDSA parameters i.e. order) */
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#define CAAM_ECDSEL_SHIFT 7
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#define CAAM_ECDSA_PD 0x00400000
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#define CAAM_ECDSA_KEYGEN_PD 0x02000000
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#define CAAM_ECDSA_P192 (0x00 << CAAM_ECDSEL_SHIFT)
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#define CAAM_ECDSA_P224 (0x01 << CAAM_ECDSEL_SHIFT)
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#define CAAM_ECDSA_P256 (0x02 << CAAM_ECDSEL_SHIFT)
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#define CAAM_ECDSA_P384 (0x03 << CAAM_ECDSEL_SHIFT)
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#define CAAM_ECDSA_P521 (0x04 << CAAM_ECDSEL_SHIFT)
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#define CAAM_ECDSA_BRAINPOOL_P256 (0x0B << CAAM_ECDSEL_SHIFT)
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/* PKHA Operation ID ECDSA */
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#define CAAM_ECDSA_KEYPAIR 0x00140000
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#define CAAM_ECDSA_SIGN 0x00150000
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#define CAAM_ECDSA_VERIFY 0x00160000
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#define CAAM_ECDSA_ECDH 0x00170000
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#define CAAM_ECDSA_MESREP_HASHED (0x10 << 7)
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/* key encryption bit */
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#define CAAM_PKHA_ECC 0x00000002
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#define CAAM_PKHA_ENC_PRI_AESCBC 0x00000004
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#define CAAM_PKHA_ENC_PRI_AESCCM (0x00000010 | CAAM_PKHA_ENC_PRI_AESCBC)
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#define CAAM_PKHA_NO_TIMING_RESISTANCE 0x40000000
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#define CAAM_LOAD_BLACK_KEY 0x500000
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/* PKHA RSA */
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#define CAAM_OPID_RSA_ENCRYPT 0x00180000
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#define CAAM_OPID_RSA_DECRYPT 0x00190000
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#define CAAM_MD5_CTXSZ (16 + 8)
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#define CAAM_SHA_CTXSZ (20 + 8)
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#define CAAM_SHA224_CTXSZ (32 + 8)
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#define CAAM_SHA256_CTXSZ (32 + 8)
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#define CAAM_SHA384_CTXSZ (64 + 8)
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#define CAAM_SHA512_CTXSZ (64 + 8)
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/* RNG 50h */
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#define CAAM_RNG 0x00500000
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/* Used to get raw entropy from TRNG */
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#define CAAM_ENTROPY 0x00500001
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#define FIFOL_TYPE_MSG 0x00100000
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#define FIFOL_TYPE_AAD 0x00300000
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#define FIFOL_TYPE_FC1 0x00010000
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#define FIFOL_TYPE_LC1 0x00020000
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#define FIFOL_TYPE_LC2 0x00040000
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#define FIFOS_TYPE_MSG 0x00300000
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/* continue bit set if more output is expected */
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#define CAAM_FIFOS_CONT 0x00800000
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#define CAAM_PAGE_SZ 4096
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/* RNG Registers */
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#define CAAM_RTMCTL 0X0600
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#define CAAM_RTSDCTL 0X0610
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#define CAAM_RTFRQMIN 0X0618
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#define CAAM_RTFRQMAX 0X061C
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#define CAAM_RDSTA 0X06C0
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#define CAAM_RTSTATUS 0x063C
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#define CAAM_RDINT0 0x06D0
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/* each of the following 11 RTENT registers are an offset of 4 from RTENT0 */
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#define CAAM_RTENT0 0x0640
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#define CAAM_RTENT11 0x066C /* Max RTENT register */
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#define CAAM_RTENT_MAX 0x067C
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/* RNG Masks/Values */
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#ifndef CAAM_ENT_DLY
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/* Less than half the default value to try and increase entropy collection.
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* Value is system clock cycles. */
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#define CAAM_ENT_DLY 1200
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#endif
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#ifndef CAAM_ENT_DLY_INCREMENT
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#define CAAM_ENT_DLY_INCREMENT 500
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#endif
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#ifndef CAAM_ENT_SAMPLE
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/* default sample value from reference manual */
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#define CAAM_ENT_SAMPLE 0x09C4
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#endif
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#ifndef CAAM_ENT_DLY_MAX
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#define CAAM_ENT_DLY_MAX 12000
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#endif
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#ifndef CAAM_ENT_MINSHIFT
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/* default to the minimum entropy delay of 1/4 */
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#define CAAM_ENT_MINSHIFT 2
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#endif
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#ifndef CAAM_ENT_MAXSHIFT
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/* default to the maximum entropy delay of 16 times */
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#define CAAM_ENT_MAXSHIFT 4
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#endif
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#define CAAM_PRGM 0x00010000 /* Set RTMCTL to program state */
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#define CAAM_TRNG 0x00000020 /* Set TRNG access */
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#define CAAM_RTMCTL_RESET 0x40 /* TRNG reset to defaults */
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#define CAAM_CTLERR 0x00001000
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#define CAAM_ENTVAL 0x00000400 /* checking RTMCTL for entropy ready */
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/* Input Job Ring Registers */
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#define CAAM_IRBAR0 0x1004
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//0x1004
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#define CAAM_IRSR0 0x100C
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#define CAAM_IRJAR0 0x101C
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#define CAAM_IRBAR2 0x3000
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#define CAAM_IRSR2 0x300C
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#define CAAM_IRJAR2 0x301C
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#define CAAM_IRSAR_JR2 0x3014
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/* Output Job Ring Registers */
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#define CAAM_ORBAR0 0x1024
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//0x1024
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#define CAAM_ORSR0 0x102C
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#define CAAM_ORJAR0 0x103C
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#define CAAM_ORBAR2 0x3024
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//0x1024
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#define CAAM_ORSR2 0x302C
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#define CAAM_ORJAR2 0x303C
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#define JRCFGR_JR0_LS 0x1054
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/* Status Registers */
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#define CAAM_STATUS 0x0FD4
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#define CAAM_VERSION_MS 0x0FE8
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#define CAAM_VERSION_LS 0x0FEC
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#define CAMM_SUPPORT_MS 0x0FF0
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#define CAMM_SUPPORT_LS 0x0FF4
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#define CAAM_SM_CMD 0x1BE4
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#define CAAM_SM_SMPO 0x1FBC
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#define CAAM_SM_SMVID_MS 0x1FD8
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#define CAAM_SM_SMVID_LS 0x1FDC
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#define CAAM_SM_STATUS 0x1BEC
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#define CAAM_SM_CSP 0x00008000
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#define CAAM_SM_SMAP_LOCK 0x00002000
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#define CAAM_SM_SMAG_LOCK 0x00001000
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#define CAAM_SM_ALL_RW 0x000000FF
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#define CAAM_C1DSR_LS 0x8014
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#define CAAM_C1MR 0x8004
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/* output FIFO is 16 entries deep and each entry has a two 4 byte registers */
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#define CAAM_FIFOO_MS 0x87F0
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#define CAAM_FIFOO_LS 0x87F4
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/* input FIFO is 16 entries deep with each entry having two 4 byte registers
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All data written to it from IP bus should be in big endian format */
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#define CAAM_FIFOI_LS 0x87E0
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/* offset of 4 with range 0 .. 13 */
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#define CAAM_CTX1 0x8100
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#define CAAM_CTRIV CAAM_CTX1 + 8 /* AES-CTR iv is in 2 and 3 */
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#define CAAM_CBCIV CAAM_CTX1 /* AES-CBC iv is in 1 and 2 */
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/* debugging registers */
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#define CAAM_DECORR 0x009C /* used to set DECO into debug mode */
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#define CAAM_DODJR 0x8E00 /* for hung operations */
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#define CAAM_DOJQCR_MS 0x8800
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#define CAAM_DOOPSTA_MS 0x8810 /* DECO operation status register */
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#define CAAM_DODAR 0x8808 /* address of current descriptor */
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#define CAAM_DODESB 0x8A00 /* 64 registers that hold the current descriptor buffer */
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#define JRINTR_JR0 0x104C
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#define JRINTR_JR1 0x204C
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#define JRINTR_JR2 0x304C
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#define CAAM_SINGLE_STEP_MODE 0x40000000
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#define CAAM_STEP 0x80000000
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/* Port layer for CAAM driver, functions defined in caam_<env>.c */
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unsigned int CAAM_READ(unsigned int reg);
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void CAAM_WRITE(unsigned int reg, unsigned int in);
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int CAAM_SET_BASEADDR(void);
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void CAAM_UNSET_BASEADDR(void);
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unsigned int CAAM_ADR_TO_PHYSICAL(void* in, int inSz);
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void* CAAM_ADR_MAP(unsigned int in, int inSz, unsigned char copy);
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void CAAM_ADR_UNMAP(void* vaddr, unsigned int out, int outSz,
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unsigned char copy);
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int CAAM_ADR_SYNC(void* vaddr, int sz);
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CAAM_ADDRESS CAAM_ADR_TO_VIRTUAL(CAAM_ADDRESS in, int length);
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#ifndef WOLFSSL_CAAM_BUFFER
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#define WOLFSSL_CAAM_BUFFER
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typedef struct CAAM_BUFFER {
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int BufferType;
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CAAM_ADDRESS TheAddress;
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int Length;
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} CAAM_BUFFER;
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#endif
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unsigned int caamReadRegister(unsigned int reg);
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void caamWriteRegister(unsigned int reg, unsigned int in);
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int SynchronousSendRequest(int type, unsigned int args[4], CAAM_BUFFER *buf, int sz);
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int CleanupCAAM(void);
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/* Driver API that can be called by caam_<env>.c port layers */
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typedef struct DESCSTRUCT DESCSTRUCT;
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int caamKeyCover(DESCSTRUCT *desc, int sz, unsigned int args[4]);
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int caamTRNG(unsigned char *out, int outSz);
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int caamECDSA_ECDH(DESCSTRUCT *desc, int sz, unsigned int args[4]);
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int caamECDSASign(DESCSTRUCT *desc, int sz, unsigned int args[4]);
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int caamECDSAVerify(DESCSTRUCT *desc, CAAM_BUFFER *buf, int sz,
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unsigned int args[4]);
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int caamECDSAMake(DESCSTRUCT *desc, CAAM_BUFFER *buf, unsigned int args[4]);
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int caamAesCmac(DESCSTRUCT *desc, int sz, unsigned int args[4]);
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int caamBlob(DESCSTRUCT *desc);
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CAAM_ADDRESS caamGetPartition(unsigned int part, int partSz, unsigned int flag);
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int caamFreePart(unsigned int part);
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int caamFindUnusuedPartition(void);
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void caamDescInit(DESCSTRUCT* desc, int type, unsigned int args[4],
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CAAM_BUFFER* buf, int sz);
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/* CAAM descriptor */
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#define DESC_COUNT 1
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#define MAX_BUF 20
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#define BUFFER_COUNT (MAX_BUF * DESC_COUNT)
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/* CAAM descriptors can only be 64 unsigned ints */
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#define MAX_DESC_SZ 64
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/* 64 byte buffer for when data crosses a page boundary */
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#define ALIGN_BUF 16
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/* MAX_CTX is 64 bytes (sha512 digest) + 8 bytes (CAAM length value) */
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#define MAX_CTX 18
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#define MIN_READ_REG CAAM_BASE
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#define MAX_READ_REG (CAAM_BASE + 0x00010000)
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struct buffer {
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CAAM_ADDRESS data;
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CAAM_ADDRESS dataSz;
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};
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struct DESCSTRUCT {
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#if defined(__INTEGRITY) || defined(INTEGRITY)
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struct IORequestStruct TheIORequest;
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#endif
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struct CAAM_DEVICE* caam;
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struct buffer buf[MAX_BUF]; /* buffers holding data input address */
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unsigned int desc[MAX_DESC_SZ]; /* max size of 64 word32 */
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unsigned int aadSzBuf[4]; /* Formatted AAD size for CCM */
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unsigned int alignBuf[ALIGN_BUF]; /* 64 byte buffer for non page
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align */
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unsigned int iv[MAX_CTX]; /* AES IV and also hash state */
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unsigned int ctxBuf[MAX_CTX]; /* key */
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CAAM_ADDRESS output; /* address to output buffer */
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CAAM_ADDRESS ctxOut; /* address to update buffer holding state */
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Value alignIdx;/* index for align buffer */
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Value idx; /* index for descriptor buffer */
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Value headIdx; /* for first portion of descriptor buffer */
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Value lastIdx; /* for last portion of descriptor buffer */
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Value outputIdx; /* idx to output buffer in "buf" */
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Value inputSz; /* size of input buffer */
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Value ctxSz; /* size of CTX/Key buffer */
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Value aadSz; /* AAD size for CCM */
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Value startIdx; /* for telling header where to start */
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Value lastFifo;
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Value type;
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Value state;
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Value DescriptorCount;
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Boolean running; /* True if building/running descriptor is
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in process */
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};
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/* wolfSSL specific flags */
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#define CAAM_FIND_PART 0xFFFFFFFF
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#define CAAM_GET_PART 0xFFFFFFFE
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#define CAAM_FREE_PART 0xFFFFFFFD
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#define CAAM_READ_PART 0xFFFFFFFC
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#define CAAM_WRITE_PART 0xFFFFFFFB
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#define MAX_ECDSA_VERIFY_ADDR 8
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#define MAX_ECDSA_SIGN_ADDR 8
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#define BLACK_KEY_MAC_SZ 16
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#define BLACK_BLOB_KEYMOD_SZ 16
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#define RED_BLOB_KEYMOD_SZ 8
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#endif /* CAAM_DRIVER_H */
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