2024-05-10 16:36:47 +02:00
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#pragma once
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#include <coreinit/debug.h>
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#include <coreinit/screen.h>
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extern "C" uint32_t __OSPhysicalToEffectiveUncached(uint32_t);
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2024-11-27 20:44:36 +01:00
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static uint32_t DCReadReg32(const OSScreenID screen, const uint32_t index) {
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2024-05-10 16:36:47 +02:00
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if (OSIsECOMode()) {
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return 0;
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}
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2024-11-27 20:44:36 +01:00
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const auto regs = reinterpret_cast<uint32_t *>(__OSPhysicalToEffectiveUncached(0xc200000));
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2024-05-10 16:36:47 +02:00
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return regs[index + (screen * 0x200)];
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}
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2024-11-27 20:44:36 +01:00
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static void DCWriteReg32(const OSScreenID screen, const uint32_t index, const uint32_t val) {
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2024-05-10 16:36:47 +02:00
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if (OSIsECOMode()) {
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return;
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}
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2024-11-27 20:44:36 +01:00
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const auto regs = reinterpret_cast<uint32_t *>(__OSPhysicalToEffectiveUncached(0xc200000));
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2024-05-10 16:36:47 +02:00
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regs[index + (screen * 0x200)] = val;
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}
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// https://www.x.org/docs/AMD/old/42589_rv630_rrg_1.01o.pdf (reg id in document / 4)
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#define D1GRPH_ENABLE_REG 0x1840
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#define D1GRPH_CONTROL_REG 0x1841
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#define D1GRPH_PITCH_REG 0x1848
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#define D1OVL_PITCH_REG 0x1866
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#define D1GRPH_X_END_REG 0x184d
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#define D1GRPH_Y_END_REG 0x184e
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2024-11-27 20:44:36 +01:00
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static void SetDCPitchReg(const OSScreenID screen, const uint16_t pitch) {
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2024-05-10 16:36:47 +02:00
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DCWriteReg32(screen, D1GRPH_PITCH_REG, pitch);
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DCWriteReg32(screen, D1OVL_PITCH_REG, pitch);
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}
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