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1a825dcfce
* check TMD for vwii_title flag for IOS WADs
268 lines
7.3 KiB
C
268 lines
7.3 KiB
C
/*
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mini - a Free Software replacement for the Nintendo/BroadOn IOS.
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SEEPROM support
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Copyright (C) 2008, 2009 Sven Peter <svenpeter@gmail.com>
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Copyright (C) 2008, 2009 Haxx Enterprises <bushing@gmail.com>
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Copyright (C) 2008, 2009 Hector Martin "marcan" <marcan@marcansoft.com>
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Copyright (C) 2008, 2009 John Kelley <wiidev@kelley.ca>
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Copyright (C) 2020 Pablo Curiel "DarkMatterCore" <pabloacurielz@gmail.com>
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# This code is licensed to you under the terms of the GNU GPL, version 2;
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# see http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
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*/
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#include <ogc/machine/processor.h>
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#include <unistd.h>
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#include <string.h>
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#include "mini_seeprom.h"
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#define HW_REG_BASE 0xd800000
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#define HW_GPIO1OUT (HW_REG_BASE + 0x0e0)
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#define HW_GPIO1IN (HW_REG_BASE + 0x0e8)
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#define HW_SEEPROM_BLK_SIZE 2
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#define HW_SEEPROM_BLK_CNT (SEEPROM_SIZE / HW_SEEPROM_BLK_SIZE)
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#define eeprom_delay() usleep(5)
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enum {
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GP_EEP_CS = 0x000400,
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GP_EEP_CLK = 0x000800,
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GP_EEP_MOSI = 0x001000,
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GP_EEP_MISO = 0x002000
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};
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static void seeprom_send_bits(u16 value, u8 bits)
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{
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if (!bits || bits > 16) return;
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while(bits--)
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{
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if (value & (1 << bits))
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{
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mask32(HW_GPIO1OUT, 0, GP_EEP_MOSI);
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} else {
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mask32(HW_GPIO1OUT, GP_EEP_MOSI, 0);
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}
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eeprom_delay();
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mask32(HW_GPIO1OUT, 0, GP_EEP_CLK);
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eeprom_delay();
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mask32(HW_GPIO1OUT, GP_EEP_CLK, 0);
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eeprom_delay();
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}
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}
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static u16 seeprom_recv_bits(u8 bits)
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{
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if (!bits || bits > 16) return 0;
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int res = 0;
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while(bits--)
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{
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res <<= 1;
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mask32(HW_GPIO1OUT, 0, GP_EEP_CLK);
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eeprom_delay();
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mask32(HW_GPIO1OUT, GP_EEP_CLK, 0);
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eeprom_delay();
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res |= !!(read32(HW_GPIO1IN) & GP_EEP_MISO);
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}
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return (u16)res;
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}
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u16 seeprom_read(void *dst, u16 offset, u16 size)
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{
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/*
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* WiiUBrew told me that you interact with the SEEPROM the exact same way you do on Wii.
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* However the contents are way different. Like there's absolutely no vWii stuff here.
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*/
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if (read16(0xCD8005A0) == 0xCAFE) return 0;
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if (!dst || offset >= SEEPROM_SIZE || !size || (offset + size) > SEEPROM_SIZE) return 0;
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u16 cur_offset = 0;
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u8 *ptr = (u8*)dst;
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u8 val[HW_SEEPROM_BLK_SIZE] = {0};
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// Calculate block offsets and sizes
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u8 start_addr = (u8)(offset / HW_SEEPROM_BLK_SIZE);
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u8 start_addr_offset = (u8)(offset % HW_SEEPROM_BLK_SIZE);
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u8 end_addr = (u8)((offset + size) / HW_SEEPROM_BLK_SIZE);
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u8 end_addr_size = (u8)((offset + size) % HW_SEEPROM_BLK_SIZE);
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if (!end_addr_size)
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{
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end_addr--;
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end_addr_size = HW_SEEPROM_BLK_SIZE;
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}
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if (end_addr == start_addr) end_addr_size -= start_addr_offset;
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mask32(HW_GPIO1OUT, GP_EEP_CLK, 0);
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mask32(HW_GPIO1OUT, GP_EEP_CS, 0);
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eeprom_delay();
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for(u16 i = start_addr; i <= end_addr; i++)
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{
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if (cur_offset >= size) break;
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// Start command cycle
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mask32(HW_GPIO1OUT, 0, GP_EEP_CS);
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// Send read command + address
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seeprom_send_bits(0x600 | i, 11);
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// Receive data
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*((u16*)val) = seeprom_recv_bits(16);
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// End of command cycle
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mask32(HW_GPIO1OUT, GP_EEP_CS, 0);
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eeprom_delay();
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// Copy read data to destination buffer
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if (i == start_addr && start_addr_offset != 0)
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{
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// Handle unaligned read at start address
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memcpy(ptr + cur_offset, val + start_addr_offset, HW_SEEPROM_BLK_SIZE - start_addr_offset);
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cur_offset += (HW_SEEPROM_BLK_SIZE - start_addr_offset);
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} else
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if (i == end_addr && end_addr_size != HW_SEEPROM_BLK_SIZE)
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{
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// Handle unaligned read at end address
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memcpy(ptr + cur_offset, val, end_addr_size);
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cur_offset += end_addr_size;
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} else {
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// Normal read
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memcpy(ptr + cur_offset, val, HW_SEEPROM_BLK_SIZE);
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cur_offset += HW_SEEPROM_BLK_SIZE;
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}
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}
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return cur_offset;
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}
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#if 0
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u16 seeprom_write(const void *src, u16 offset, u16 size)
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{
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if (!src || offset >= SEEPROM_SIZE || !size || (offset + size) > SEEPROM_SIZE) return 0;
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u32 level = 0;
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u16 cur_offset = 0;
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const u8 *ptr = (const u8*)src;
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u8 val[HW_SEEPROM_BLK_SIZE] = {0};
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// Calculate block offsets and sizes
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u8 start_addr = (u8)(offset / HW_SEEPROM_BLK_SIZE);
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u8 start_addr_offset = (u8)(offset % HW_SEEPROM_BLK_SIZE);
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u8 end_addr = (u8)((offset + size) / HW_SEEPROM_BLK_SIZE);
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u8 end_addr_size = (u8)((offset + size) % HW_SEEPROM_BLK_SIZE);
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if (!end_addr_size)
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{
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end_addr--;
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end_addr_size = HW_SEEPROM_BLK_SIZE;
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}
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if (end_addr == start_addr) end_addr_size -= start_addr_offset;
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// Disable CPU interruptions
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_CPU_ISR_Disable(level);
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mask32(HW_GPIO1OUT, GP_EEP_CLK, 0);
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mask32(HW_GPIO1OUT, GP_EEP_CS, 0);
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eeprom_delay();
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// EWEN - Enable programming commands
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mask32(HW_GPIO1OUT, 0, GP_EEP_CS);
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seeprom_send_bits(0x4FF, 11);
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mask32(HW_GPIO1OUT, GP_EEP_CS, 0);
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eeprom_delay();
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for(u16 i = start_addr; i <= end_addr; i++)
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{
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if (cur_offset >= size) break;
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// Copy data to write from source buffer
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if ((i == start_addr && start_addr_offset != 0) || (i == end_addr && end_addr_size != HW_SEEPROM_BLK_SIZE))
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{
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// Read data from SEEPROM to handle unaligned writes
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// Start command cycle
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mask32(HW_GPIO1OUT, 0, GP_EEP_CS);
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// Send read command + address
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seeprom_send_bits(0x600 | i, 11);
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// Receive data
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*((u16*)val) = seeprom_recv_bits(16);
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// End of command cycle
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mask32(HW_GPIO1OUT, GP_EEP_CS, 0);
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eeprom_delay();
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if (i == start_addr && start_addr_offset != 0)
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{
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// Handle unaligned write at start address
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memcpy(val + start_addr_offset, ptr + cur_offset, HW_SEEPROM_BLK_SIZE - start_addr_offset);
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cur_offset += (HW_SEEPROM_BLK_SIZE - start_addr_offset);
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} else {
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// Handle unaligned write at end address
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memcpy(val, ptr + cur_offset, end_addr_size);
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cur_offset += end_addr_size;
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}
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} else {
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// Normal write
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memcpy(val, ptr + cur_offset, HW_SEEPROM_BLK_SIZE);
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cur_offset += HW_SEEPROM_BLK_SIZE;
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}
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// Start command cycle
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mask32(HW_GPIO1OUT, 0, GP_EEP_CS);
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// Send write command + address
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seeprom_send_bits(0x500 | i, 11);
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// Send data
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seeprom_send_bits(*((u16*)val), 16);
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// End of command cycle
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mask32(HW_GPIO1OUT, GP_EEP_CS, 0);
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eeprom_delay();
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// Wait until SEEPROM is ready (write cycle is self-timed so no clocking needed)
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mask32(HW_GPIO1OUT, 0, GP_EEP_CS);
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do {
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eeprom_delay();
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} while(!(read32(HW_GPIO1IN) & GP_EEP_MISO));
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mask32(HW_GPIO1OUT, GP_EEP_CS, 0);
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eeprom_delay();
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}
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// EWDS - Disable programming commands
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mask32(HW_GPIO1OUT, 0, GP_EEP_CS);
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seeprom_send_bits(0x400, 11);
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mask32(HW_GPIO1OUT, GP_EEP_CS, 0);
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eeprom_delay();
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// Enable CPU interruptions
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_CPU_ISR_Restore(level);
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return cur_offset;
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}
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#endif
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