213 lines
2.9 KiB
ArmAsm
213 lines
2.9 KiB
ArmAsm
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.global _start
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.global start
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.global udelay
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.global RegWrite
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.global RegRead
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.global DRAMWrite
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.global DRAMRead
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.global DRAMCTRLRead
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.global DRAMCTRLWrite
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.extern main
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.extern Syscall
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.extern SWI
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.extern PrefetchAbort
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.extern DataAbort
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.extern IRQHandler
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.extern FIQHandler
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.arm
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.section ".init"
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_start:
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ldr pc, =start
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ldr pc, =Syscall
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ldr pc, =SWI
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ldr pc, =PrefetchAbort
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ldr pc, =DataAbort
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ldr pc, =0
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ldr pc, =IRQHandler
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movs pc, lr
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start:
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mov r0, #0
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ldr r1, =0xd80003c
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str r0, [r1]
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mov r0, #0
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mcr p15, 0, r0,c7,c5
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mcr p15, 0, r0,c7,c6
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mrc p15, 0, r0,c1,c0
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bic r0, r0, #4
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bic r0, r0, #0x1000
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mcr p15, 0, r0,c1,c0
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ldr r0,=__bss_start
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ldr r1,=__bss_end
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mov r2,#0
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mov r3,#4
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clearbss:
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cmp r0, r1
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bcs clearbss_end
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str r2, [r0], r3
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b clearbss
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clearbss_end:
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msr CPSR_c, #211
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ldr sp, =0xFFFF7E60
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msr CPSR_c, #210
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ldr sp, =0xFFFF7E60
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msr CPSR_c, #209
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ldr sp, =0xFFFF7E60
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msr CPSR_c, #215
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ldr sp, =0xFFFF7E60
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msr CPSR_c, #219
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ldr sp, =0xFFFF7E60
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msr CPSR_c, #31
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ldr sp, =0xFFFE4000
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#enable IRQs
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mrs r1, cpsr
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bic r1, r1, #0xC0
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msr cpsr_c, r1
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mov lr, pc
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ldr pc, =main
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RegWrite:
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ldr r3,=0xd8b4000
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lsl r0, r0, #1
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add r0, r0, r3
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strh r1, [r0]
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bx lr
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RegRead:
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ldr r3,=0xd8b4000
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lsl r0, r0, #1
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add r0, r0, r3
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ldrh r0, [r0]
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lsl r0, r0, #0x10
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lsr r0, r0, #0x10
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bx lr
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DRAMWrite:
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push {r4,lr}
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add r3, r0, #0
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add r4, r1, #0
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mov r0, #0x3a
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add r1, r3, #0
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bl RegWrite
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mov r0, #0x3a
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bl RegRead
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mov r0, #0x3b
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add r1, r4, #0
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bl RegWrite
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pop {r4}
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pop {r0}
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bx r0
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DRAMRead:
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push {lr}
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add r1, r0, #0
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mov r0, #0x3a
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bl RegWrite
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mov r0, #0x3a
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bl RegRead
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mov r0, #0x3b
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bl RegRead
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pop {r1}
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bx r1
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DRAMCTRLWrite:
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push {r4,r5,lr}
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ldr r4, =0x163
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add r3, r0, #0
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add r5, r1, #0
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add r0, r4, #0
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add r1, r3, #0
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bl DRAMWrite
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add r0, r4, #0
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bl DRAMRead
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mov r0, #0xb1
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add r1, r5, #0
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lsl r0, r0, #1
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bl DRAMWrite
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pop {r4,r5}
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pop {r0}
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bx r0
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DRAMCTRLRead:
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push {r4,lr}
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ldr r4, =0x163
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add r1, r0, #0
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add r0, r4, #0
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bl DRAMWrite
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add r0, r4, #0
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bl DRAMRead
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ldr r0, =0x162
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bl DRAMRead
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pop {r4}
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pop {r1}
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bx r1
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udelay:
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push {lr}
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lsr r3, r0, #2
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add r3, r3, r0
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lsr r2, r0, #6
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add r0, r3, r2
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cmp r0, #1
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bhi loc_ffff20e8
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mov r0, #2
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loc_ffff20e8:
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ldr r1, =0xd800010
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ldr r3, [r1]
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add r2, r3, r0
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cmp r2, r3
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bls loc_ffff211c
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loc_ffff20f2:
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ldr r3, [r1]
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cmp r3, r2
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bcc loc_ffff20f2
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loc_ffff20f8:
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pop {r0}
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bx r0
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loc_ffff211c:
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add r3, r1, #0
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loc_ffff211e:
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ldr r0, [r3]
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cmp r0, #0
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blt loc_ffff211e
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cmp r0, r2
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bcc loc_ffff211e
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b loc_ffff20f8
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.end
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