89 lines
2.0 KiB
C
89 lines
2.0 KiB
C
#ifndef _HW_
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#define _HW_
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#include "string.h"
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#include "global.h"
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#include "memory.h"
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#include "alloc.h"
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#include "dip.h"
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#include "GCPad.h"
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#define P2C(x) ((x)&0x7FFFFFFF)
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#define HW_BASE 0x0d800000
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#define HW_MEMIRR (HW_BASE+0x60)
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#define HW_AHBPROT (HW_BASE+0x64)
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#define HW_DDRCTRL_ADDR (HW_BASE+0x74)
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#define HW_DDRCTRL_VAL (HW_BASE+0x76)
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#define HW_GPIO_ENABLE (HW_BASE+0xDC)
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#define HW_GPIO_OUT (HW_BASE+0xE0)
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#define HW_GPIO_DIR (HW_BASE+0xE4)
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#define HW_GPIO_IN (HW_BASE+0xE8)
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#define HW_GPIO_INTLVL (HW_BASE+0xEC)
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#define HW_GPIO_INTFLAG (HW_BASE+0xF0)
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#define HW_GPIO_INTMASK (HW_BASE+0xF4)
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#define HW_GPIO_INMIR (HW_BASE+0xF8)
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#define HW_GPIO_OWNER (HW_BASE+0xFC)
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#define HW_ACRPLLSYS (HW_BASE+0x1B0)
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#define HW_ACRPLLSYSEXT (HW_BASE+0x1B4)
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#define DIFLAGS_PPCBOOT (1<<20)
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#define IRQ_TIMER (1<<0)
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#define IRQ_NAND (1<<1)
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#define IRQ_AES (1<<2)
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#define IRQ_SHA1 (1<<3)
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#define IRQ_EHCI (1<<4)
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#define IRQ_OHCI0 (1<<5)
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#define IRQ_OHCI1 (1<<6)
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#define IRQ_SDHC (1<<7)
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#define IRQ_WIFI (1<<8)
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#define IRQ_GPIO1B (1<<10)
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#define IRQ_GPIO1 (1<<11)
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#define IRQ_RESET (1<<17)
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#define IRQ_PPCIPC (1<<30)
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#define IRQ_IPC (1<<31)
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#define GPIO_POWER (1<<1)
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#define GPIO_EJECT (1<<9)
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extern void DRAMCTRLWrite( u32 Register, u32 Value );
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extern u32 DRAMCTRLRead( u32 Register );
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void EHCIInit( void );
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void EXIControl( u32 value );
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void MIOSHWInit( u32 A, u32 B );
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void MIOSInit( void );
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void MEMInitLow( void );
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void BootPPC( void );
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void UNKInit( u32 A, u32 B );
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void DRAMInit( u32 A, u32 B );
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void ChangeClock( void );
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void PPCReset( void );
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void HWResetDisable( void );
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void HWResetEnable( void );
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void HW_184( void );
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void HW_184_2( void );
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void GetRevision( u32 *Version, u32 *Revision );
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void HWMAgic( u32 R0, u32 R1, u32 R2, u32 R3 );
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u32 DRAMRead( u32 ValueA );
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void DRAMWrite( u32 ValueA, u32 ValueB );
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u32 RegRead( u32 Register );
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void RegWrite( u32 Register, u32 Value );
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void HWRegWriteBatch( u32 A, u32 B, u32 C, u32 D, u32 delay );
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void Shutdown( void );
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#endif
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