283 lines
9.7 KiB
C
283 lines
9.7 KiB
C
/*
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* Copyright (c) 2009 Kwiirk
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* Original Copyright (c) 2001-2002 by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "ehci_types.h"
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#ifndef __LINUX_EHCI_HCD_H
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#define __LINUX_EHCI_HCD_H
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/* definitions used for the EHCI driver */
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/*
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* __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
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* __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
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* the host controller implementation.
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*
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* To facilitate the strongest possible byte-order checking from "sparse"
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* and so on, we use __leXX unless that's not practical.
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*/
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#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
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typedef __u32 __bitwise __hc32;
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typedef __u16 __bitwise __hc16;
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#else
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#define __hc32 __le32
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#define __hc16 __le16
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#endif
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#define EHCI_MAX_ROOT_PORTS 4 /* see HCS_N_PORTS */
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#define EHCI_MAX_QTD 8
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#include "usb.h"
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struct ehci_device{
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usb_devdesc desc;
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int id;
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int port;
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int fd;
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u32 toggles;
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};
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#define ep_bit(ep) (((ep)&0xf)+(((ep)>>7)?16:0))
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#define get_toggle(dev,ep) (((dev)->toggles>>ep_bit(ep))&1)
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#define set_toggle(dev,ep,v) (dev)->toggles = ((dev)->toggles &(~(1<<ep_bit(ep)))) | ((v)<<ep_bit(ep))
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struct ehci_urb{
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void* setup_buffer;
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dma_addr_t setup_dma;
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void* transfer_buffer;
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dma_addr_t transfer_dma;
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u32 transfer_buffer_length;
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u32 actual_length;
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u8 ep;
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u8 input;
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u32 maxpacket;
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};
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struct ehci_hcd { /* one per controller */
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/* glue to PCI and HCD framework */
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void __iomem *_regs;
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struct ehci_caps __iomem *caps;
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struct ehci_regs __iomem *regs;
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struct ehci_dbg_port __iomem *debug;
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void *device;
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__u32 hcs_params; /* cached register copy */
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/* async schedule support */
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struct ehci_qh *async; // the head never gets a qtd inside.
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struct ehci_qh *asyncqh;
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struct ehci_qtd *qtds[EHCI_MAX_QTD];
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int qtd_used;
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unsigned long next_statechange;
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u32 command;
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/* HW need periodic table initialised even if we dont use it @todo:is it really true? */
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#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
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__hc32 *periodic; /* hw periodic table */
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dma_addr_t periodic_dma;
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u8 num_port;
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struct ehci_device devices[EHCI_MAX_ROOT_PORTS]; /* the attached device list per port */
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void *ctrl_buffer; /* pre allocated buffer for control messages */
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};
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/*-------------------------------------------------------------------------*/
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#include "ehci_defs.h"
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/*-------------------------------------------------------------------------*/
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#define QTD_NEXT( dma) cpu_to_hc32( (u32)dma)
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/*
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* EHCI Specification 0.95 Section 3.5
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* QTD: describe data transfer components (buffer, direction, ...)
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* See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
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*
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* These are associated only with "QH" (Queue Head) structures,
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* used with control, bulk, and interrupt transfers.
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*/
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struct ehci_qtd {
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/* first part defined by EHCI spec */
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__hc32 hw_next; /* see EHCI 3.5.1 */
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__hc32 hw_alt_next; /* see EHCI 3.5.2 */
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__hc32 hw_token; /* see EHCI 3.5.3 */
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#define QTD_TOGGLE (1 << 31) /* data toggle */
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#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
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#define QTD_IOC (1 << 15) /* interrupt on complete */
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#define QTD_CERR(tok) (((tok)>>10) & 0x3)
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#define QTD_PID(tok) (((tok)>>8) & 0x3)
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#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
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#define QTD_STS_HALT (1 << 6) /* halted on error */
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#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
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#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
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#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
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#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
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#define QTD_STS_STS (1 << 1) /* split transaction state */
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#define QTD_STS_PING (1 << 0) /* issue PING? */
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#define ACTIVE_BIT(ehci) cpu_to_hc32( QTD_STS_ACTIVE)
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#define HALT_BIT(ehci) cpu_to_hc32( QTD_STS_HALT)
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#define STATUS_BIT(ehci) cpu_to_hc32( QTD_STS_STS)
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__hc32 hw_buf [5]; /* see EHCI 3.5.4 */
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__hc32 hw_buf_hi [5]; /* Appendix B */
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/* the rest is HCD-private */
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dma_addr_t qtd_dma; /* qtd address */
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struct ehci_qtd *next; /* sw qtd list */
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struct ehci_urb *urb; /* qtd's urb */
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size_t length; /* length of buffer */
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} __attribute__ ((aligned (32)));
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/* mask NakCnt+T in qh->hw_alt_next */
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#define QTD_MASK(ehci) cpu_to_hc32 ( ~0x1f)
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#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
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/*-------------------------------------------------------------------------*/
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/* type tag from {qh,itd,sitd,fstn}->hw_next */
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#define Q_NEXT_TYPE(dma) ((dma) & cpu_to_hc32( 3 << 1))
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/*
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* Now the following defines are not converted using the
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* __constant_cpu_to_le32() macro anymore, since we have to support
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* "dynamic" switching between be and le support, so that the driver
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* can be used on one system with SoC EHCI controller using big-endian
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* descriptors as well as a normal little-endian PCI EHCI controller.
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*/
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/* values for that type tag */
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#define Q_TYPE_ITD (0 << 1)
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#define Q_TYPE_QH (1 << 1)
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#define Q_TYPE_SITD (2 << 1)
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#define Q_TYPE_FSTN (3 << 1)
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/* next async queue entry, or pointer to interrupt/periodic QH */
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#define QH_NEXT(dma) (cpu_to_hc32( (((u32)dma)&~0x01f)|Q_TYPE_QH))
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/* for periodic/async schedules and qtd lists, mark end of list */
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#define EHCI_LIST_END() cpu_to_hc32( 1) /* "null pointer" to hw */
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/*
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* Entries in periodic shadow table are pointers to one of four kinds
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* of data structure. That's dictated by the hardware; a type tag is
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* encoded in the low bits of the hardware's periodic schedule. Use
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* Q_NEXT_TYPE to get the tag.
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*
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* For entries in the async schedule, the type tag always says "qh".
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*/
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union ehci_shadow {
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struct ehci_qh *qh; /* Q_TYPE_QH */
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struct ehci_itd *itd; /* Q_TYPE_ITD */
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struct ehci_sitd *sitd; /* Q_TYPE_SITD */
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struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
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__hc32 *hw_next; /* (all types) */
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void *ptr;
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};
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/*-------------------------------------------------------------------------*/
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/*
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* EHCI Specification 0.95 Section 3.6
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* QH: describes control/bulk/interrupt endpoints
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* See Fig 3-7 "Queue Head Structure Layout".
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*
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* These appear in both the async and (for interrupt) periodic schedules.
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*/
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struct ehci_qh {
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/* first part defined by EHCI spec */
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__hc32 hw_next; /* see EHCI 3.6.1 */
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__hc32 hw_info1; /* see EHCI 3.6.2 */
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#define QH_HEAD 0x00008000
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__hc32 hw_info2; /* see EHCI 3.6.2 */
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#define QH_SMASK 0x000000ff
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#define QH_CMASK 0x0000ff00
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#define QH_HUBADDR 0x007f0000
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#define QH_HUBPORT 0x3f800000
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#define QH_MULT 0xc0000000
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__hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
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/* qtd overlay (hardware parts of a struct ehci_qtd) */
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__hc32 hw_qtd_next;
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__hc32 hw_alt_next;
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__hc32 hw_token;
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__hc32 hw_buf [5];
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__hc32 hw_buf_hi [5];
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/* the rest is HCD-private */
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dma_addr_t qh_dma; /* address of qh */
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struct ehci_qtd *qtd_head; /* sw qtd list */
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struct ehci_hcd *ehci;
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#define NO_FRAME ((unsigned short)~0) /* pick new start */
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} __attribute__ ((aligned (32)));
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/*-------------------------------------------------------------------------*/
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/*-------------------------------------------------------------------------*/
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/* cpu to ehci */
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#define cpu_to_hc32(b) cpu_to_le32(b)
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#define hc32_to_cpu(b) le32_to_cpu(b)
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#define hc32_to_cpup(b) le32_to_cpu(*(b))
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/*-------------------------------------------------------------------------*/
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/* os specific functions */
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void*ehci_maligned(int size,int alignement,int crossing);
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dma_addr_t ehci_virt_to_dma(void *);
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dma_addr_t ehci_dma_map_to(void *buf,size_t len);
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dma_addr_t ehci_dma_map_from(void *buf,size_t len);
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dma_addr_t ehci_dma_map_bidir(void *buf,size_t len);
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void ehci_dma_unmap_to(dma_addr_t buf,size_t len);
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void ehci_dma_unmap_from(dma_addr_t buf,size_t len);
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void ehci_dma_unmap_bidir(dma_addr_t buf,size_t len);
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/* extern API */
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s32 ehci_control_message(struct ehci_device *dev,u8 bmRequestType,u8 bmRequest,u16 wValue,u16 wIndex,u16 wLength,void *buf);
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s32 ehci_bulk_message(struct ehci_device *dev,u8 bEndpoint,u16 wLength,void *rpData);
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int ehci_discover(void);
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int ehci_get_device_list(u8 maxdev,u8 b0,u8*num,u16*buf);
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extern struct ehci_hcd *ehci; /* @todo put ehci as a static global and remove ehci from APIs.. */
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extern int ehci_open_device(int vid,int pid,int fd);
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extern int ehci_close_device(struct ehci_device *dev);
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extern void * ehci_fd_to_dev(int fd);
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extern int ehci_release_ports(void);
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/* UMS API */
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s32 USBStorage_Init(void);
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s32 USBStorage_Get_Capacity(u32*sector_size);
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s32 USBStorage_Read_Sectors(u32 sector, u32 numSectors, void *buffer);
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s32 USBStorage_Read_Stress(u32 sector, u32 numSectors, void *buffer);
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s32 USBStorage_Write_Sectors(u32 sector, u32 numSectors, const void *buffer);
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#ifndef DEBUG
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#define STUB_DEBUG_FILES
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#endif /* DEBUG */
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/*-------------------------------------------------------------------------*/
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#endif /* __LINUX_EHCI_HCD_H */
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