From f6131e9703ecee6440367817f8f21e215f776735 Mon Sep 17 00:00:00 2001
From: Tillmann Karras <tilkax@gmail.com>
Date: Wed, 29 Nov 2023 05:49:02 +0000
Subject: [PATCH] Jit64: fix invalid instruction encoding

This is a recent regression introduced in
c70dcf99dd7b434d5196feb47f2a6e87bb34234b.
---
 Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp
index c7cadd2a3b..7d5db65e47 100644
--- a/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp
+++ b/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp
@@ -585,7 +585,7 @@ void Jit64::mcrxr(UGeckoInstruction inst)
 
   // Clear XER[0-3]
   static_assert(PPCSTATE_OFF(xer_ca) + 1 == PPCSTATE_OFF(xer_so_ov));
-  MOV(16, PPCSTATE(xer_ca), Imm8(0));
+  MOV(16, PPCSTATE(xer_ca), Imm16(0));
 }
 
 void Jit64::crXXX(UGeckoInstruction inst)