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JitArm64: Reserve W30 in SafeStoreFromReg and stfXX

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Bug introduced in c45028a7081f872e87c9d9b42f70f3086aa912f7.

EmitBackpatchRoutine assumes that X30 is available as a temporary.
This commit is contained in:
MerryMage 2017-04-15 08:20:14 +01:00
parent 3fb886141d
commit 03d07c36ae
2 changed files with 4 additions and 4 deletions
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4
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp
View File

@ -141,7 +141,7 @@ void JitArm64::SafeLoadToReg(u32 dest, s32 addr, s32 offsetReg, u32 flags, s32 o
void JitArm64::SafeStoreFromReg(s32 dest, u32 value, s32 regOffset, u32 flags, s32 offset)
{
// We want to make sure to not get LR as a temp register
gpr.Lock(W0, W1);
gpr.Lock(W0, W1, W30);
ARM64Reg RS = gpr.R(value);
@ -282,7 +282,7 @@ void JitArm64::SafeStoreFromReg(s32 dest, u32 value, s32 regOffset, u32 flags, s
EmitBackpatchRoutine(flags, jo.fastmem, jo.fastmem, RS, XA, regs_in_use, fprs_in_use);
}
gpr.Unlock(W0, W1);
gpr.Unlock(W0, W1, W30);
}
void JitArm64::lXX(UGeckoInstruction inst)

4
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp
View File

@ -241,7 +241,7 @@ void JitArm64::stfXX(UGeckoInstruction inst)
u32 imm_addr = 0;
bool is_immediate = false;
gpr.Lock(W0, W1);
gpr.Lock(W0, W1, W30);
fpr.Lock(Q0);
bool single = (flags & BackPatchInfo::FLAG_SIZE_F32) && fpr.IsSingle(inst.FS, true);
@ -398,6 +398,6 @@ void JitArm64::stfXX(UGeckoInstruction inst)
{
EmitBackpatchRoutine(flags, jo.fastmem, jo.fastmem, V0, XA, regs_in_use, fprs_in_use);
}
gpr.Unlock(W0, W1);
gpr.Unlock(W0, W1, W30);
fpr.Unlock(Q0);
}