The-Homebrew-Cloud/dolphin
2
0
Fork 0
mirror of https://github.com/dolphin-emu/dolphin.git synced 2025-01-10 16:19:28 +01:00
Code Issues Packages Projects Releases Wiki Activity

Implemented jit'ing of floating point compare operations in the IL

Browse Source 
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3312 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
LinesPrower 2009-06-03 13:14:03 +00:00
parent b46e8ab1b8
commit 074fe9c9ea
3 changed files with 27 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
Source/Core/Core/Src/PowerPC/Jit64IL/IR.cpp
View File

@ -257,6 +257,10 @@ InstLoc IRBuilder::FoldZeroOp(unsigned Opcode, unsigned extra) {
FRegCache[extra] = EmitZeroOp(LoadFReg, extra); FRegCache[extra] = EmitZeroOp(LoadFReg, extra);
return FRegCache[extra]; return FRegCache[extra];
} }
if (Opcode == LoadFRegDENToZero) {
// cant use cache here
return EmitZeroOp(LoadFRegDENToZero, extra);
}
if (Opcode == LoadCarry) { if (Opcode == LoadCarry) {
if (!CarryCache) if (!CarryCache)
CarryCache = EmitZeroOp(LoadCarry, extra); CarryCache = EmitZeroOp(LoadCarry, extra);
@ -1313,6 +1317,7 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
case LoadCTR: case LoadCTR:
case LoadMSR: case LoadMSR:
case LoadFReg: case LoadFReg:
case LoadFRegDENToZero:
case LoadGQR: case LoadGQR:
case BlockEnd: case BlockEnd:
case BlockStart: case BlockStart:
@ -1982,6 +1987,22 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
RI.fregs[reg] = I; RI.fregs[reg] = I;
break; break;
} }
case LoadFRegDENToZero: {
if (!thisUsed) break;
X64Reg reg = fregFindFreeReg(RI);
unsigned ppcreg = *I >> 8;
char *p = (char*)&(PowerPC::ppcState.ps[ppcreg][0]);
Jit->MOV(32, R(ECX), M(p+4));
Jit->AND(32, R(ECX), Imm32(0x7ff00000));
Jit->CMP(32, R(ECX), Imm32(0x38000000));
FixupBranch ok = Jit->J_CC(CC_AE);
Jit->AND(32, M(p+4), Imm32(0x80000000));
Jit->MOV(32, M(p), Imm32(0));
Jit->SetJumpTarget(ok);
Jit->MOVAPD(reg, M(&PowerPC::ppcState.ps[ppcreg]));
RI.fregs[reg] = I;
break;
}
case StoreFReg: { case StoreFReg: {
unsigned ppcreg = *I >> 16; unsigned ppcreg = *I >> 16;
Jit->MOVAPD(M(&PowerPC::ppcState.ps[ppcreg]), Jit->MOVAPD(M(&PowerPC::ppcState.ps[ppcreg]),

4
Source/Core/Core/Src/PowerPC/Jit64IL/IR.h
View File

@ -119,6 +119,7 @@ namespace IREmitter {
ExpandPackedToMReg, ExpandPackedToMReg,
CompactMRegToPacked, CompactMRegToPacked,
LoadFReg, LoadFReg,
LoadFRegDENToZero,
FSMul, FSMul,
FSAdd, FSAdd,
FSSub, FSSub,
@ -411,6 +412,9 @@ namespace IREmitter {
InstLoc EmitLoadFReg(unsigned freg) { InstLoc EmitLoadFReg(unsigned freg) {
return FoldZeroOp(LoadFReg, freg); return FoldZeroOp(LoadFReg, freg);
} }
InstLoc EmitLoadFRegDENToZero(unsigned freg) {
return FoldZeroOp(LoadFRegDENToZero, freg);
}
InstLoc EmitStoreFReg(InstLoc val, unsigned freg) { InstLoc EmitStoreFReg(InstLoc val, unsigned freg) {
return FoldUOp(StoreFReg, val, freg); return FoldUOp(StoreFReg, val, freg);
} }

7
Source/Core/Core/Src/PowerPC/Jit64IL/Jit_FloatingPoint.cpp
View File

@ -102,14 +102,11 @@
void Jit64::fcmpx(UGeckoInstruction inst) void Jit64::fcmpx(UGeckoInstruction inst)
{ {
// @TODO: conform this to the new fcmpo
Default(inst); return;
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(FloatingPoint) JITDISABLE(FloatingPoint)
IREmitter::InstLoc lhs, rhs, res; IREmitter::InstLoc lhs, rhs, res;
lhs = ibuild.EmitLoadFReg(inst.FA); lhs = ibuild.EmitLoadFRegDENToZero(inst.FA);
rhs = ibuild.EmitLoadFReg(inst.FB); rhs = ibuild.EmitLoadFRegDENToZero(inst.FB);
res = ibuild.EmitFDCmpCR(lhs, rhs); res = ibuild.EmitFDCmpCR(lhs, rhs);
ibuild.EmitStoreFPRF(res); ibuild.EmitStoreFPRF(res);
ibuild.EmitStoreCR(res, inst.CRFD); ibuild.EmitStoreCR(res, inst.CRFD);