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Implemented jit'ing of floating point compare operations in the IL
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3312 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -257,6 +257,10 @@ InstLoc IRBuilder::FoldZeroOp(unsigned Opcode, unsigned extra) {
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FRegCache[extra] = EmitZeroOp(LoadFReg, extra);
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return FRegCache[extra];
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}
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if (Opcode == LoadFRegDENToZero) {
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// cant use cache here
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return EmitZeroOp(LoadFRegDENToZero, extra);
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}
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if (Opcode == LoadCarry) {
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if (!CarryCache)
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CarryCache = EmitZeroOp(LoadCarry, extra);
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@ -1313,6 +1317,7 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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case LoadCTR:
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case LoadMSR:
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case LoadFReg:
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case LoadFRegDENToZero:
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case LoadGQR:
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case BlockEnd:
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case BlockStart:
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@ -1982,6 +1987,22 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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RI.fregs[reg] = I;
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break;
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}
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case LoadFRegDENToZero: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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unsigned ppcreg = *I >> 8;
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char *p = (char*)&(PowerPC::ppcState.ps[ppcreg][0]);
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Jit->MOV(32, R(ECX), M(p+4));
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Jit->AND(32, R(ECX), Imm32(0x7ff00000));
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Jit->CMP(32, R(ECX), Imm32(0x38000000));
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FixupBranch ok = Jit->J_CC(CC_AE);
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Jit->AND(32, M(p+4), Imm32(0x80000000));
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Jit->MOV(32, M(p), Imm32(0));
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Jit->SetJumpTarget(ok);
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Jit->MOVAPD(reg, M(&PowerPC::ppcState.ps[ppcreg]));
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RI.fregs[reg] = I;
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break;
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}
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case StoreFReg: {
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unsigned ppcreg = *I >> 16;
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Jit->MOVAPD(M(&PowerPC::ppcState.ps[ppcreg]),
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@ -119,6 +119,7 @@ namespace IREmitter {
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ExpandPackedToMReg,
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CompactMRegToPacked,
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LoadFReg,
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LoadFRegDENToZero,
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FSMul,
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FSAdd,
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FSSub,
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@ -411,6 +412,9 @@ namespace IREmitter {
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InstLoc EmitLoadFReg(unsigned freg) {
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return FoldZeroOp(LoadFReg, freg);
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}
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InstLoc EmitLoadFRegDENToZero(unsigned freg) {
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return FoldZeroOp(LoadFRegDENToZero, freg);
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}
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InstLoc EmitStoreFReg(InstLoc val, unsigned freg) {
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return FoldUOp(StoreFReg, val, freg);
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}
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@ -102,14 +102,11 @@
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void Jit64::fcmpx(UGeckoInstruction inst)
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{
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// @TODO: conform this to the new fcmpo
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Default(inst); return;
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INSTRUCTION_START
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JITDISABLE(FloatingPoint)
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IREmitter::InstLoc lhs, rhs, res;
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lhs = ibuild.EmitLoadFReg(inst.FA);
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rhs = ibuild.EmitLoadFReg(inst.FB);
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lhs = ibuild.EmitLoadFRegDENToZero(inst.FA);
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rhs = ibuild.EmitLoadFRegDENToZero(inst.FB);
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res = ibuild.EmitFDCmpCR(lhs, rhs);
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ibuild.EmitStoreFPRF(res);
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ibuild.EmitStoreCR(res, inst.CRFD);
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