From 0a606d73565963fcdc4f5d7f209c61853e5bf1d0 Mon Sep 17 00:00:00 2001
From: Marko Pusljar <LM1234@gmail.com>
Date: Sat, 14 Aug 2010 09:07:28 +0000
Subject: [PATCH] fixes for my previous commits

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6095 8ced0084-cf51-0410-be5f-012b33b47a6e
---
 Source/Core/DSPCore/Src/DSPCore.h        |  2 +-
 Source/Core/DSPCore/Src/DSPIntExtOps.cpp | 10 +++-------
 Source/Core/DSPCore/Src/DSPIntUtil.h     | 22 ++++++----------------
 Source/DSPSpy/dspregs.h                  |  5 +++--
 4 files changed, 13 insertions(+), 26 deletions(-)

diff --git a/Source/Core/DSPCore/Src/DSPCore.h b/Source/Core/DSPCore/Src/DSPCore.h
index aa14272447..92cb8516bf 100644
--- a/Source/Core/DSPCore/Src/DSPCore.h
+++ b/Source/Core/DSPCore/Src/DSPCore.h
@@ -163,7 +163,7 @@
 #define SR_INT_ENABLE		0x0200 // Not 100% sure but duddie says so. This should replace the hack, if so.
 #define SR_400				0x0400 // unknown
 #define SR_EXT_INT_ENABLE	0x0800 // Appears in zelda - seems to disable external interupts
-#define SR_ROUNDING_MODE	0x1000 // 0 - convergent rounding, 1 - twos complement rounding (source: motorola DSP56?00FM.pdf-s)
+#define SR_1000				0x1000 // unknown
 #define SR_MUL_MODIFY		0x2000 // 1 = normal. 0 = x2   (M0, M2)
 #define SR_40_MODE_BIT		0x4000 // 0 = "16", 1 = "40"  (SET16, SET40)  Controls sign extension when loading mid accums.
 #define SR_MUL_UNSIGNED		0x8000 // 0 = normal. 1 = unsigned  (CLR15, SET15) If set, treats operands as unsigned. Tested with mulx only so far.
diff --git a/Source/Core/DSPCore/Src/DSPIntExtOps.cpp b/Source/Core/DSPCore/Src/DSPIntExtOps.cpp
index 0928d57af7..0486d2a238 100644
--- a/Source/Core/DSPCore/Src/DSPIntExtOps.cpp
+++ b/Source/Core/DSPCore/Src/DSPIntExtOps.cpp
@@ -74,12 +74,7 @@ void mv(const UDSPInstruction opc)
  	u8 sreg = (opc & 0x3) + DSP_REG_ACL0;
 	u8 dreg = ((opc >> 2) & 0x3);
 
-#if 0 //more tests 
-	if ((sreg >= DSP_REG_ACM0) && (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT)) 
-		writeToBackLog(0, dreg + DSP_REG_AXL0, ((u16)dsp_get_acc_h(sreg-DSP_REG_ACM0) & 0x0080) ? 0x8000 : 0x7fff);
-	else
-#endif	
-		writeToBackLog(0, dreg + DSP_REG_AXL0, g_dsp.r[sreg]);
+	writeToBackLog(0, dreg + DSP_REG_AXL0, g_dsp.r[sreg]);
 }
 	
 // S @$arD, $acS.S
@@ -475,7 +470,8 @@ void zeroWriteBackLog()
 	}
 }
 
-//needed for 0x3... 
+//needed for 0x3... cases when main and extended are modifying the same ACC 
+//games are not doing that + in motorola (similar dsp) dox this is forbidden to do
 //ex. corner case -> 0x3060: main opcode modifies .m, and extended .l -> .l shoudnt be zeroed because of .m write...
 void zeroWriteBackLogPreserveAcc(u8 acc) 
 {
diff --git a/Source/Core/DSPCore/Src/DSPIntUtil.h b/Source/Core/DSPCore/Src/DSPIntUtil.h
index fa0c0e3ebe..8e8e286ff7 100644
--- a/Source/Core/DSPCore/Src/DSPIntUtil.h
+++ b/Source/Core/DSPCore/Src/DSPIntUtil.h
@@ -214,15 +214,10 @@ inline s64 dsp_get_long_prod_round_prodl()
 {
 	s64 prod = dsp_get_long_prod();
 	
-	if (g_dsp.r[DSP_REG_SR] & SR_ROUNDING_MODE)
+	if (prod & 0x10000)
 		prod = (prod + 0x8000) & ~0xffff;
-	else 
-	{
-		if (prod & 0x10000)
-			prod = (prod + 0x8000) & ~0xffff;
-		else
-			prod = (prod + 0x7fff) & ~0xffff;
-	}
+	else
+		prod = (prod + 0x7fff) & ~0xffff;
 
 	return prod;
 }
@@ -280,15 +275,10 @@ inline s64 dsp_convert_long_acc(s64 val) // s64 -> s40
 
 inline s64 dsp_round_long_acc(s64 val)
 {
-	if (g_dsp.r[DSP_REG_SR] & SR_ROUNDING_MODE)
+	if (val & 0x10000)
 		val = (val + 0x8000) & ~0xffff;
-	else 
-	{
-		if (val & 0x10000)
-			val = (val + 0x8000) & ~0xffff;
-		else
-			val = (val + 0x7fff) & ~0xffff;
-	}
+	else
+		val = (val + 0x7fff) & ~0xffff;
 
 	return val;
 }
diff --git a/Source/DSPSpy/dspregs.h b/Source/DSPSpy/dspregs.h
index a5f1d2c473..e9a96c1a6f 100644
--- a/Source/DSPSpy/dspregs.h
+++ b/Source/DSPSpy/dspregs.h
@@ -17,7 +17,6 @@
 
 #ifndef _DSPREGS_H
 #define _DSPREGS_H
-#endif
 
 #define DSP_REG_AR0		0x00 // address registers
 #define DSP_REG_AR1		0x01
@@ -60,4 +59,6 @@
 #define DSP_REG_ACM0	0x1e // Mid accumulator
 #define DSP_REG_ACM1	0x1f
 #define DSP_REG_ACH0	0x10 // Sign extended 8 bit register 0
-#define DSP_REG_ACH1	0x11 // Sign extended 8 bit register 1
\ No newline at end of file
+#define DSP_REG_ACH1	0x11 // Sign extended 8 bit register 1
+
+#endif
\ No newline at end of file