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JitArm64: Move memcheck check into fallback code.

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So now each implemented slowmem instruction should check for DSI on each own.
This commit is contained in:
degasus 2016-09-11 15:34:51 +02:00
parent 39c08694a0
commit 11bfc7fe77
1 changed files with 20 additions and 20 deletions
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40
Source/Core/Core/PowerPC/JitArm64/Jit.cpp
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@ -120,6 +120,26 @@ void JitArm64::FallBackToInterpreter(UGeckoInstruction inst)
SetJumpTarget(c); SetJumpTarget(c);
} }
} }
if (jo.memcheck && (js.op->opinfo->flags & FL_LOADSTORE))
{
ARM64Reg WA = gpr.GetReg();
LDR(INDEX_UNSIGNED, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
FixupBranch noException = TBZ(WA, IntLog2(EXCEPTION_DSI));
FixupBranch handleException = B();
SwitchToFarCode();
SetJumpTarget(handleException);
gpr.Flush(FLUSH_MAINTAIN_STATE);
fpr.Flush(FLUSH_MAINTAIN_STATE);
WriteExceptionExit(js.compilerPC);
SwitchToNearCode();
SetJumpTarget(noException);
gpr.Unlock(WA);
}
} }
void JitArm64::HLEFunction(UGeckoInstruction inst) void JitArm64::HLEFunction(UGeckoInstruction inst)
@ -598,26 +618,6 @@ const u8* JitArm64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer* code_buf, JitB
// If we have a register that will never be used again, flush it. // If we have a register that will never be used again, flush it.
gpr.StoreRegisters(~ops[i].gprInUse); gpr.StoreRegisters(~ops[i].gprInUse);
fpr.StoreRegisters(~ops[i].fprInUse); fpr.StoreRegisters(~ops[i].fprInUse);
if (jo.memcheck && (opinfo->flags & FL_LOADSTORE))
{
ARM64Reg WA = gpr.GetReg();
LDR(INDEX_UNSIGNED, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
FixupBranch noException = TBZ(WA, IntLog2(EXCEPTION_DSI));
FixupBranch handleException = B();
SwitchToFarCode();
SetJumpTarget(handleException);
gpr.Flush(FLUSH_MAINTAIN_STATE);
fpr.Flush(FLUSH_MAINTAIN_STATE);
WriteExceptionExit(js.compilerPC);
SwitchToNearCode();
SetJumpTarget(noException);
gpr.Unlock(WA);
}
} }
i += js.skipInstructions; i += js.skipInstructions;