mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-01-09 07:39:26 +01:00
3 more activated instructions in the jit = maybe 1% more speed ;P
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@163 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
hrydgard
parent
e3d21c0b11
commit
12b37ba323
@ -391,7 +391,7 @@ void CInterpreter::srawix(UGeckoInstruction _inst)
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void CInterpreter::srwx(UGeckoInstruction _inst)
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{
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u32 amount = m_GPR[_inst.RB];
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m_GPR[_inst.RA] = (amount&0x20) ? 0 : m_GPR[_inst.RS] >> amount;
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m_GPR[_inst.RA] = (amount & 0x20) ? 0 : (m_GPR[_inst.RS] >> amount);
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if (_inst.Rc) Helper_UpdateCR0(m_GPR[_inst.RA]);
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}
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@ -147,6 +147,8 @@ namespace Jit64
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void rlwinmx(UGeckoInstruction inst);
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void rlwimix(UGeckoInstruction inst);
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void rlwnmx(UGeckoInstruction inst);
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void negx(UGeckoInstruction inst);
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void slwx(UGeckoInstruction inst);
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void srwx(UGeckoInstruction inst);
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void dcbz(UGeckoInstruction inst);
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void lfsx(UGeckoInstruction inst);
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@ -67,7 +67,7 @@ namespace Jit64
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}
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else
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{
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_assert_msg_(DYNA_REC,0,"WTF");
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_assert_msg_(DYNA_REC, 0, "WTF");
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}
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if (Rc)
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{
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@ -93,10 +93,10 @@ namespace Jit64
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case 25: regimmop(a, s, true, inst.UIMM << 16, Or, OR, false); break;//oris
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case 28: regimmop(a, s, true, inst.UIMM, And, AND, true); break;
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case 29: regimmop(a, s, true, inst.UIMM << 16, And, AND, true); break;
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case 26: regimmop(a, s, true, inst.UIMM, Xor, XOR, false); break; //xori
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case 27: regimmop(a, s, true, inst.UIMM << 16, Xor, XOR, false); break; //xoris
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case 12: //addic
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case 13: //addic_rc
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case 26: //xori
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case 27: //xoris
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default:
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Default(inst);
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break;
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@ -633,7 +633,6 @@ namespace Jit64
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}
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u32 mask = Helper_Mask(inst.MB, inst.ME);
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gpr.FlushR(ECX);
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gpr.LockX(ECX);
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gpr.Lock(a, b, s);
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@ -652,21 +651,34 @@ namespace Jit64
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}
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}
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void negx(UGeckoInstruction inst)
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{
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INSTRUCTION_START;
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int a = inst.RA;
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int d = inst.RD;
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gpr.Lock(a, d);
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gpr.LoadToX64(d, a == d, true);
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if (a != d)
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MOV(32, gpr.R(d), gpr.R(a));
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NEG(32, gpr.R(d));
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gpr.UnlockAll();
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if (inst.Rc)
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{
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MOV(32, R(EAX), gpr.R(a));
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CALL((u8*)Asm::computeRc);
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}
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}
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void srwx(UGeckoInstruction inst)
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{
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INSTRUCTION_START;
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// BUGGY?
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Default(inst); return;
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int a = inst.RA;
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int b = inst.RB;
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int s = inst.RS;
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gpr.FlushR(ECX);
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gpr.LockX(ECX);
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gpr.Lock(a, b, s);
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if (a == s)
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gpr.LoadToX64(a, true, true);
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else
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gpr.LoadToX64(a, false, true);
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gpr.LoadToX64(a, a == s || a == b || s == b, true);
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MOV(32, R(ECX), gpr.R(b));
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AND(32, R(ECX), Imm8(63));
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XOR(32, R(EAX), R(EAX));
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@ -685,6 +697,34 @@ namespace Jit64
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}
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}
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void slwx(UGeckoInstruction inst)
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{
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INSTRUCTION_START;
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int a = inst.RA;
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int b = inst.RB;
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int s = inst.RS;
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gpr.FlushR(ECX);
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gpr.LockX(ECX);
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gpr.Lock(a, b, s);
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gpr.LoadToX64(a, a == s || a == b || s == b, true);
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MOV(32, R(ECX), gpr.R(b));
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AND(32, R(ECX), Imm8(63));
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XOR(32, R(EAX), R(EAX));
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TEST(32, R(ECX), Imm32(32));
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FixupBranch branch = J_CC(CC_NZ);
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MOV(32, R(EAX), gpr.R(s));
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SHL(32, R(EAX), R(ECX));
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SetJumpTarget(branch);
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MOV(32, gpr.R(a), R(EAX));
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gpr.UnlockAll();
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gpr.UnlockAllX();
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if (inst.Rc)
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{
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MOV(32, R(EAX), gpr.R(a));
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CALL((u8*)Asm::computeRc);
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}
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}
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// another crazy instruction :(
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void srawix(UGeckoInstruction inst)
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{
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@ -93,6 +93,7 @@ void lfs(UGeckoInstruction inst)
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gpr.UnlockAll();
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fpr.UnlockAll();
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}
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void lfd(UGeckoInstruction inst)
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{
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INSTRUCTION_START;
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@ -112,8 +113,7 @@ void lfd(UGeckoInstruction inst)
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MOV(64, M(&temp64), R(EAX));
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fpr.Lock(d);
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fpr.LoadToX64(d, false);
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MOVSD(fpr.RX(d), M(&temp64));
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MOVDDUP(fpr.RX(d), fpr.R(d));
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MOVDDUP(fpr.RX(d), M(&temp64));
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gpr.UnlockAll();
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fpr.UnlockAll();
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}
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@ -155,8 +155,8 @@ GekkoOPTemplate primarytable[] =
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{24, CInterpreter::ori, Jit64::reg_imm, {"ori", OPTYPE_INTEGER, 0}},
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{25, CInterpreter::oris, Jit64::reg_imm, {"oris", OPTYPE_INTEGER, 0}},
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{26, CInterpreter::xori, Jit64::Default, {"xori", OPTYPE_INTEGER, 0}},
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{27, CInterpreter::xoris, Jit64::Default, {"xoris", OPTYPE_INTEGER, 0}},
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{26, CInterpreter::xori, Jit64::reg_imm, {"xori", OPTYPE_INTEGER, 0}},
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{27, CInterpreter::xoris, Jit64::reg_imm, {"xoris", OPTYPE_INTEGER, 0}},
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{28, CInterpreter::andi_rc, Jit64::reg_imm, {"andi_rc", OPTYPE_INTEGER, FL_SET_CR0}},
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{29, CInterpreter::andis_rc, Jit64::reg_imm, {"andis_rc", OPTYPE_INTEGER, FL_SET_CR0}},
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@ -291,7 +291,7 @@ GekkoOPTemplate table31[] =
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{536, CInterpreter::srwx, Jit64::srwx, {"srwx", OPTYPE_INTEGER, FL_RC_BIT}},
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{792, CInterpreter::srawx, Jit64::Default, {"srawx", OPTYPE_INTEGER, FL_RC_BIT}},
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{824, CInterpreter::srawix, Jit64::srawix, {"srawix", OPTYPE_INTEGER, FL_RC_BIT}},
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{24, CInterpreter::slwx, Jit64::Default, {"slwx", OPTYPE_INTEGER, FL_RC_BIT}},
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{24, CInterpreter::slwx, Jit64::slwx, {"slwx", OPTYPE_INTEGER, FL_RC_BIT}},
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{54, CInterpreter::dcbst, Jit64::Default, {"dcbst", OPTYPE_DCACHE, 0, 4}},
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{86, CInterpreter::dcbf, Jit64::Default, {"dcbf", OPTYPE_DCACHE, 0, 4}},
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@ -396,7 +396,7 @@ GekkoOPTemplate table31_2[] =
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{75, CInterpreter::mulhwx, Jit64::Default, {"mulhwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT, 4}},
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{11, CInterpreter::mulhwux, Jit64::mulhwux, {"mulhwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT, 4}},
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{235, CInterpreter::mullwx, Jit64::mullwx, {"mullwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT, 4}},
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{104, CInterpreter::negx, Jit64::Default, {"negx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT}},
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{104, CInterpreter::negx, Jit64::negx, {"negx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT}},
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{40, CInterpreter::subfx, Jit64::subfx, {"subfx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT}},
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{8, CInterpreter::subfcx, Jit64::Default, {"subfcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_SET_CA | FL_RC_BIT}},
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{136, CInterpreter::subfex, Jit64::Default, {"subfex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
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