From 13051ee2912d27f757d16b72fe4eb423ea2e3d4e Mon Sep 17 00:00:00 2001 From: Pokechu22 Date: Thu, 15 Jul 2021 11:30:37 -0700 Subject: [PATCH] docs/DSP: Elaborate on SBSET and SBCLR --- .../GameCube_DSP_Users_Manual.tex | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex b/docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex index 12ea60a361..9272431ffa 100644 --- a/docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex +++ b/docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex @@ -2921,11 +2921,11 @@ There are two pairs of conditions that work similarly: \texttt{EQ}/\texttt{NE} a \end{DSPOpcodeFormat} \begin{DSPOpcodeDescription} - \item Set bit of status register \Register{\$sr}. Bit number is calculated by adding 6 to immediate value \Value{I}. + \item Set bit of status register \Register{\$sr}. Bit number is calculated by adding 6 to immediate value \Value{I}; thus, bits 6 through 13 (\texttt{LZ} through \texttt{AM}) can be set with this instruction. \end{DSPOpcodeDescription} \begin{DSPOpcodeOperation} - $sr |= (I + 6) + $sr |= 1 << (I + 6) $pc++ \end{DSPOpcodeOperation} \end{DSPOpcode} @@ -2940,11 +2940,11 @@ There are two pairs of conditions that work similarly: \texttt{EQ}/\texttt{NE} a \end{DSPOpcodeFormat} \begin{DSPOpcodeDescription} - \item Clear bit of status register \Register{\$sr}. Bit number is calculated by adding 6 to immediate value \Value{I}. + \item Clear bit of status register \Register{\$sr}. Bit number is calculated by adding 6 to immediate value \Value{I}; thus, bits 6 through 13 (\texttt{LZ} through \texttt{AM}) can be cleared with this instruction. \end{DSPOpcodeDescription} \begin{DSPOpcodeOperation} - $sr &= ~(I + 6) + $sr &= ~(1 << (I + 6)) $pc++ \end{DSPOpcodeOperation} \end{DSPOpcode}