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DSPInterpreter: Fix IsLess
`IsLess` would incorrectly return true if both `SR_OVERFLOW` and `SR_SIGN` are set, as `(sr & SR_OVERFLOW) != (sr & SR_SIGN)` becomes `SR_OVERFLOW != SR_SIGN` which is true as the two masks are different. This broke in e651592ef56521f6db71f8a671fe8c20b948d338. This issue only affected the DSP LLE Interpreter, and not the DSP LLE JIT. I've also included a simple test case for this. `ax0.l` (on the top left) is set to 0 if the instruction following `IFL` does not execute and to 1 if it is executed.
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@ -250,10 +250,7 @@ bool Interpreter::CheckCondition(u8 condition) const
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const auto IsCarry = [this] { return IsSRFlagSet(SR_CARRY); };
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const auto IsCarry = [this] { return IsSRFlagSet(SR_CARRY); };
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const auto IsOverflow = [this] { return IsSRFlagSet(SR_OVERFLOW); };
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const auto IsOverflow = [this] { return IsSRFlagSet(SR_OVERFLOW); };
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const auto IsOverS32 = [this] { return IsSRFlagSet(SR_OVER_S32); };
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const auto IsOverS32 = [this] { return IsSRFlagSet(SR_OVER_S32); };
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const auto IsLess = [this] {
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const auto IsLess = [this] { return IsSRFlagSet(SR_OVERFLOW) != IsSRFlagSet(SR_SIGN); };
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const auto& state = m_dsp_core.DSPState();
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return (state.r.sr & SR_OVERFLOW) != (state.r.sr & SR_SIGN);
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};
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const auto IsZero = [this] { return IsSRFlagSet(SR_ARITH_ZERO); };
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const auto IsZero = [this] { return IsSRFlagSet(SR_ARITH_ZERO); };
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const auto IsLogicZero = [this] { return IsSRFlagSet(SR_LOGIC_ZERO); };
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const auto IsLogicZero = [this] { return IsSRFlagSet(SR_LOGIC_ZERO); };
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const auto IsConditionA = [this] {
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const auto IsConditionA = [this] {
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16
Source/DSPSpy/tests/less_test.ds
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16
Source/DSPSpy/tests/less_test.ds
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@ -0,0 +1,16 @@
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incdir "tests"
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include "dsp_base.inc"
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CLR $acc0
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CLR $acc1
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LRI $ac0.h, #0x0050
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LRI $ac1.h, #0x0050
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ADD $acc0, $acc1 ; Causes acc0 to overflow, and thus also become negative
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LRI $AX0.L, #0x0000
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IFL
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LRI $AX0.L, #0x0001
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CALL send_back
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; We're done, DO NOT DELETE THIS LINE
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JMP end_of_test
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