diff --git a/Source/Core/DSPCore/Src/DSPHWInterface.cpp b/Source/Core/DSPCore/Src/DSPHWInterface.cpp
index 9c0d631aeb..7bfd7cf467 100644
--- a/Source/Core/DSPCore/Src/DSPHWInterface.cpp
+++ b/Source/Core/DSPCore/Src/DSPHWInterface.cpp
@@ -158,7 +158,7 @@ void gdsp_ifx_write(u16 addr, u16 val)
 
 	    default:
 			if ((addr & 0xff) >= 0xa0) {
-				if (pdlabels[(addr & 0xFF) - 0xa0].name) {
+				if (pdlabels[(addr & 0xFF) - 0xa0].name && pdlabels[(addr & 0xFF) - 0xa0].description) {
 		   			INFO_LOG(DSPLLE, "%04x MW %s (%04x)\n", g_dsp.pc, pdlabels[(addr & 0xFF) - 0xa0].name, val);
 				}
 				else {
@@ -198,7 +198,7 @@ u16 gdsp_ifx_read(u16 addr)
 
 	    default:
 			if ((addr & 0xff) >= 0xa0) {
-				if (pdlabels[(addr & 0xFF) - 0xa0].name) {
+				if (pdlabels[(addr & 0xFF) - 0xa0].name && pdlabels[(addr & 0xFF) - 0xa0].description) {
 	   				INFO_LOG(DSPLLE, "%04x MR %s (%04x)\n", g_dsp.pc, pdlabels[(addr & 0xFF) - 0xa0].name, gdsp_ifx_regs[addr & 0xFF]);
 				}
 				else {
diff --git a/Source/Core/DSPCore/Src/DSPTables.cpp b/Source/Core/DSPCore/Src/DSPTables.cpp
index 45ca3d4f7d..4913e0cc60 100644
--- a/Source/Core/DSPCore/Src/DSPTables.cpp
+++ b/Source/Core/DSPCore/Src/DSPTables.cpp
@@ -368,43 +368,43 @@ const pdlabel_t pdlabels[] =
 	{0xffae, "COEF_A1_7", "COEF_A1_7",},
 	{0xffaf, "COEF_A2_7", "COEF_A2_7",},
 
-	{0xffb0, 0, 0,},
-	{0xffb1, 0, 0,},
-	{0xffb2, 0, 0,},
-	{0xffb3, 0, 0,},
-	{0xffb4, 0, 0,},
-	{0xffb5, 0, 0,},
-	{0xffb6, 0, 0,},
-	{0xffb7, 0, 0,},
-	{0xffb8, 0, 0,},
-	{0xffb9, 0, 0,},
-	{0xffba, 0, 0,},
-	{0xffbb, 0, 0,},
-	{0xffbc, 0, 0,},
-	{0xffbd, 0, 0,},
-	{0xffbe, 0, 0,},
-	{0xffbf, 0, 0,},
+	{0xffb0, "0xffb0", 0,},
+	{0xffb1, "0xffb1", 0,},
+	{0xffb2, "0xffb2", 0,},
+	{0xffb3, "0xffb3", 0,},
+	{0xffb4, "0xffb4", 0,},
+	{0xffb5, "0xffb5", 0,},
+	{0xffb6, "0xffb6", 0,},
+	{0xffb7, "0xffb7", 0,},
+	{0xffb8, "0xffb8", 0,},
+	{0xffb9, "0xffb9", 0,},
+	{0xffba, "0xffba", 0,},
+	{0xffbb, "0xffbb", 0,},
+	{0xffbc, "0xffbc", 0,},
+	{0xffbd, "0xffbd", 0,},
+	{0xffbe, "0xffbe", 0,},
+	{0xffbf, "0xffbf", 0,},
 
-	{0xffc0, 0, 0,},
-	{0xffc1, 0, 0,},
-	{0xffc2, 0, 0,},
-	{0xffc3, 0, 0,},
-	{0xffc4, 0, 0,},
-	{0xffc5, 0, 0,},
-	{0xffc6, 0, 0,},
-	{0xffc7, 0, 0,},
-	{0xffc8, 0, 0,},
+	{0xffc0, "0xffc0", 0,},
+	{0xffc1, "0xffc1", 0,},
+	{0xffc2, "0xffc2", 0,},
+	{0xffc3, "0xffc3", 0,},
+	{0xffc4, "0xffc4", 0,},
+	{0xffc5, "0xffc5", 0,},
+	{0xffc6, "0xffc6", 0,},
+	{0xffc7, "0xffc7", 0,},
+	{0xffc8, "0xffc8", 0,},
 	{0xffc9, "DSCR", "DSP DMA Control Reg",},
-	{0xffca, 0, 0,},
+	{0xffca, "0xffca", 0,},
 	{0xffcb, "DSBL", "DSP DMA Block Length",},
-	{0xffcc, 0, 0,},
+	{0xffcc, "0xffcc", 0,},
 	{0xffcd, "DSPA", "DSP DMA DMEM Address",},
 	{0xffce, "DSMAH", "DSP DMA Mem Address H",},
 	{0xffcf, "DSMAL", "DSP DMA Mem Address L",},
 
-	{0xffd0, 0,0,},
+	{0xffd0, "0xffd0",0,},
 	{0xffd1, "SampleFormat", "SampleFormat",},
-	{0xffd2, 0,0,},
+	{0xffd2, "0xffd2",0,},
 	{0xffd3, "UnkZelda", "Unk Zelda reads/writes from/to it",},
 	{0xffd4, "ACSAH", "Accelerator start address H",},
 	{0xffd5, "ACSAL", "Accelerator start address L",},
@@ -417,36 +417,36 @@ const pdlabel_t pdlabels[] =
 	{0xffdc, "yn2", "yn2",},
 	{0xffdd, "ARAM", "Direct Read from ARAM (uses ADPCM)",},
 	{0xffde, "GAIN", "Gain",},
-	{0xffdf, 0,0,},
+	{0xffdf, "0xffdf", 0,},
 
-	{0xffe0, 0,0,},
-	{0xffe1, 0,0,},
-	{0xffe2, 0,0,},
-	{0xffe3, 0,0,},
-	{0xffe4, 0,0,},
-	{0xffe5, 0,0,},
-	{0xffe6, 0,0,},
-	{0xffe7, 0,0,},
-	{0xffe8, 0,0,},
-	{0xffe9, 0,0,},
-	{0xffea, 0,0,},
-	{0xffeb, 0,0,},
-	{0xffec, 0,0,},
-	{0xffed, 0,0,},
-	{0xffee, 0,0,},
+	{0xffe0, "0xffe0",0,},
+	{0xffe1, "0xffe1",0,},
+	{0xffe2, "0xffe2",0,},
+	{0xffe3, "0xffe3",0,},
+	{0xffe4, "0xffe4",0,},
+	{0xffe5, "0xffe5",0,},
+	{0xffe6, "0xffe6",0,},
+	{0xffe7, "0xffe7",0,},
+	{0xffe8, "0xffe8",0,},
+	{0xffe9, "0xffe9",0,},
+	{0xffea, "0xffea",0,},
+	{0xffeb, "0xffeb",0,},
+	{0xffec, "0xffec",0,},
+	{0xffed, "0xffed",0,},
+	{0xffee, "0xffee",0,},
 	{0xffef, "AMDM", "ARAM DMA Request Mask",},
 
-	{0xfff0, 0,0,},
-	{0xfff1, 0,0,},
-	{0xfff2, 0,0,},
-	{0xfff3, 0,0,},
-	{0xfff4, 0,0,},
-	{0xfff5, 0,0,},
-	{0xfff6, 0,0,},
-	{0xfff7, 0,0,},
-	{0xfff8, 0,0,},
-	{0xfff9, 0,0,},
-	{0xfffa, 0,0,},
+	{0xfff0, "0xfff0",0,},
+	{0xfff1, "0xfff1",0,},
+	{0xfff2, "0xfff2",0,},
+	{0xfff3, "0xfff3",0,},
+	{0xfff4, "0xfff4",0,},
+	{0xfff5, "0xfff5",0,},
+	{0xfff6, "0xfff6",0,},
+	{0xfff7, "0xfff7",0,},
+	{0xfff8, "0xfff8",0,},
+	{0xfff9, "0xfff9",0,},
+	{0xfffa, "0xfffa",0,},
 	{0xfffb, "DIRQ", "DSP IRQ Request",},
 	{0xfffc, "DMBH", "DSP Mailbox H",},
 	{0xfffd, "DMBL", "DSP Mailbox L",},