From 1a52fdf7e361b26eb1b7a0ae551b9672947b9b09 Mon Sep 17 00:00:00 2001 From: Sintendo Date: Thu, 19 Nov 2020 21:25:11 +0100 Subject: [PATCH] Jit64: rlwnmx - Optimize rotate by constant Only removes the scratch register and a MOV, but hey. Before: B9 02 00 00 00 mov ecx,2 41 8B F5 mov esi,r13d D3 C6 rol esi,cl 83 E6 01 and esi,1 After: 41 8B F5 mov esi,r13d C1 C6 02 rol esi,2 83 E6 01 and esi,1 --- .../Core/Core/PowerPC/Jit64/Jit_Integer.cpp | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp index 608e588bad..0e04f574a5 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp @@ -1729,6 +1729,25 @@ void Jit64::rlwnmx(UGeckoInstruction inst) { gpr.SetImmediate32(a, Common::RotateLeft(gpr.Imm32(s), gpr.Imm32(b) & 0x1F) & mask); } + else if (gpr.IsImm(b)) + { + u32 amount = gpr.Imm32(b) & 0x1f; + RCX64Reg Ra = gpr.Bind(a, RCMode::Write); + RCOpArg Rs = gpr.Use(s, RCMode::Read); + RegCache::Realize(Ra, Rs); + + if (a != s) + MOV(32, Ra, Rs); + + if (amount) + ROL(32, Ra, Imm8(amount)); + + // we need flags if we're merging the branch + if (inst.Rc && CheckMergedBranch(0)) + AND(32, Ra, Imm32(mask)); + else + AndWithMask(Ra, mask); + } else { RCX64Reg ecx = gpr.Scratch(ECX); // no register choice