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Jit_SystemRegisters: mtspr
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@ -219,26 +219,32 @@ void Jit64::mtspr(UGeckoInstruction inst)
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break;
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break;
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case SPR_XER:
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case SPR_XER:
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gpr.Lock(d);
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{
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gpr.BindToRegister(d, true, false);
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RCX64Reg Rd = gpr.Bind(d, RCMode::Read);
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MOV(32, R(RSCRATCH), gpr.R(d));
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RegCache::Realize(Rd);
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MOV(32, R(RSCRATCH), Rd);
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AND(32, R(RSCRATCH), Imm32(0xff7f));
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AND(32, R(RSCRATCH), Imm32(0xff7f));
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MOV(16, PPCSTATE(xer_stringctrl), R(RSCRATCH));
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MOV(16, PPCSTATE(xer_stringctrl), R(RSCRATCH));
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MOV(32, R(RSCRATCH), gpr.R(d));
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MOV(32, R(RSCRATCH), Rd);
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SHR(32, R(RSCRATCH), Imm8(XER_CA_SHIFT));
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SHR(32, R(RSCRATCH), Imm8(XER_CA_SHIFT));
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AND(8, R(RSCRATCH), Imm8(1));
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AND(8, R(RSCRATCH), Imm8(1));
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MOV(8, PPCSTATE(xer_ca), R(RSCRATCH));
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MOV(8, PPCSTATE(xer_ca), R(RSCRATCH));
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MOV(32, R(RSCRATCH), gpr.R(d));
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MOV(32, R(RSCRATCH), Rd);
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SHR(32, R(RSCRATCH), Imm8(XER_OV_SHIFT));
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SHR(32, R(RSCRATCH), Imm8(XER_OV_SHIFT));
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MOV(8, PPCSTATE(xer_so_ov), R(RSCRATCH));
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MOV(8, PPCSTATE(xer_so_ov), R(RSCRATCH));
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gpr.UnlockAll();
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return;
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return;
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}
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case SPR_HID0:
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case SPR_HID0:
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{
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{
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MOV(32, R(RSCRATCH), gpr.R(d));
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RCOpArg Rd = gpr.Use(d, RCMode::Read);
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RegCache::Realize(Rd);
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MOV(32, R(RSCRATCH), Rd);
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BTR(32, R(RSCRATCH), Imm8(31 - 20)); // ICFI
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BTR(32, R(RSCRATCH), Imm8(31 - 20)); // ICFI
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MOV(32, PPCSTATE(spr[iIndex]), R(RSCRATCH));
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MOV(32, PPCSTATE(spr[iIndex]), R(RSCRATCH));
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FixupBranch dont_reset_icache = J_CC(CC_NC);
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FixupBranch dont_reset_icache = J_CC(CC_NC);
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@ -255,13 +261,9 @@ void Jit64::mtspr(UGeckoInstruction inst)
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}
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}
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// OK, this is easy.
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// OK, this is easy.
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if (!gpr.R(d).IsImm())
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RCOpArg Rd = gpr.BindOrImm(d, RCMode::Read);
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{
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RegCache::Realize(Rd);
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gpr.Lock(d);
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MOV(32, PPCSTATE(spr[iIndex]), Rd);
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gpr.BindToRegister(d, true, false);
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}
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MOV(32, PPCSTATE(spr[iIndex]), gpr.R(d));
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gpr.UnlockAll();
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}
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}
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void Jit64::mfspr(UGeckoInstruction inst)
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void Jit64::mfspr(UGeckoInstruction inst)
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