diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
index 9454a14fc3..a8e3e16d77 100644
--- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
+++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
@@ -392,9 +392,9 @@ void Interpreter::mtspr(UGeckoInstruction inst)
     // Total fake, we ignore that DMAs take time.
     if (DMAL.DMA_T)
     {
-      const u32 mem_address = DMAU.MEM_ADDR << 5;
+      const u32 mem_address = DMAU(PowerPC::ppcState).MEM_ADDR << 5;
       const u32 cache_address = DMAL.LC_ADDR << 5;
-      u32 length = ((DMAU.DMA_LEN_U << 2) | DMAL.DMA_LEN_L);
+      u32 length = ((DMAU(PowerPC::ppcState).DMA_LEN_U << 2) | DMAL.DMA_LEN_L);
 
       if (length == 0)
         length = 128;
diff --git a/Source/Core/Core/PowerPC/PowerPC.h b/Source/Core/Core/PowerPC/PowerPC.h
index d36f5ab2e3..9c60fc4287 100644
--- a/Source/Core/Core/PowerPC/PowerPC.h
+++ b/Source/Core/Core/PowerPC/PowerPC.h
@@ -238,7 +238,7 @@ void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst);
 #define HID0(ppc_state) ((UReg_HID0&)(ppc_state).spr[SPR_HID0])
 #define HID2(ppc_state) ((UReg_HID2&)(ppc_state).spr[SPR_HID2])
 #define HID4(ppc_state) ((UReg_HID4&)(ppc_state).spr[SPR_HID4])
-#define DMAU (*(UReg_DMAU*)&PowerPC::ppcState.spr[SPR_DMAU])
+#define DMAU(ppc_state) (*(UReg_DMAU*)&(ppc_state).spr[SPR_DMAU])
 #define DMAL (*(UReg_DMAL*)&PowerPC::ppcState.spr[SPR_DMAL])
 #define MMCR0 ((UReg_MMCR0&)PowerPC::ppcState.spr[SPR_MMCR0])
 #define MMCR1 ((UReg_MMCR1&)PowerPC::ppcState.spr[SPR_MMCR1])