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Jit_Integer: mullwx

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This commit is contained in:
MerryMage 2018-10-15 21:01:00 +01:00
parent 02deaab6ee
commit 24aadd933e
1 changed files with 21 additions and 17 deletions
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38
Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
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@ -1063,42 +1063,46 @@ void Jit64::mullwx(UGeckoInstruction inst)
JITDISABLE(bJITIntegerOff);
int a = inst.RA, b = inst.RB, d = inst.RD;
if (gpr.R(a).IsImm() && gpr.R(b).IsImm())
if (gpr.IsImm(a, b))
{
s32 i = gpr.R(a).SImm32(), j = gpr.R(b).SImm32();
s32 i = gpr.SImm32(a), j = gpr.SImm32(b);
gpr.SetImmediate32(d, i * j);
if (inst.OE)
GenerateConstantOverflow((s64)i * (s64)j);
}
else if (gpr.IsImm(a) || gpr.IsImm(b))
{
u32 imm = gpr.IsImm(a) ? gpr.Imm32(a) : gpr.Imm32(b);
int src = gpr.IsImm(a) ? b : a;
MultiplyImmediate(imm, src, d, inst.OE);
if (inst.OE)
GenerateOverflow();
}
else
{
gpr.Lock(a, b, d);
gpr.BindToRegister(d, (d == a || d == b), true);
/*if (gpr.R(a).IsImm() || gpr.R(b).IsImm())
RCOpArg Ra = gpr.Use(a, RCMode::Read);
RCOpArg Rb = gpr.Use(b, RCMode::Read);
RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
RegCache::Realize(Ra, Rb, Rd);
if (d == a)
{
u32 imm = gpr.R(a).IsImm() ? gpr.R(a).Imm32() : gpr.R(b).Imm32();
int src = gpr.R(a).IsImm() ? b : a;
MultiplyImmediate(imm, src, d, inst.OE);
}
else*/ if (d == a)
{
IMUL(32, gpr.RX(d), gpr.R(b));
IMUL(32, Rd, Rb);
}
else if (d == b)
{
IMUL(32, gpr.RX(d), gpr.R(a));
IMUL(32, Rd, Ra);
}
else
{
MOV(32, gpr.R(d), gpr.R(b));
IMUL(32, gpr.RX(d), gpr.R(a));
MOV(32, Rd, Rb);
IMUL(32, Rd, Ra);
}
if (inst.OE)
GenerateOverflow();
}
if (inst.Rc)
ComputeRC(gpr.R(d));
gpr.UnlockAll();
ComputeRC(d);
}
void Jit64::mulhwXx(UGeckoInstruction inst)