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Merge pull request #1593 from lioncash/arm

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Arm(64)Emitter: Make some variables static
This commit is contained in:
Lioncash 2014-11-26 07:56:21 -05:00
commit 25492f3d70
2 changed files with 48 additions and 46 deletions
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16
Source/Core/Common/Arm64Emitter.cpp
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@ -71,7 +71,7 @@ void ARM64XEmitter::FlushIcacheSection(u8* start, u8* end)
// Exception generation
const u32 ExcEnc[][3] = {
static const u32 ExcEnc[][3] = {
{0, 0, 1}, // SVC
{0, 0, 2}, // HVC
{0, 0, 3}, // SMC
@ -83,13 +83,13 @@ const u32 ExcEnc[][3] = {
};
// Arithmetic generation
const u32 ArithEnc[] = {
static const u32 ArithEnc[] = {
0x058, // ADD
0x258, // SUB
};
// Conditional Select
const u32 CondSelectEnc[][2] = {
static const u32 CondSelectEnc[][2] = {
{0, 0}, // CSEL
{0, 1}, // CSINC
{1, 0}, // CSINV
@ -97,7 +97,7 @@ const u32 CondSelectEnc[][2] = {
};
// Data-Processing (1 source)
const u32 Data1SrcEnc[][2] = {
static const u32 Data1SrcEnc[][2] = {
{0, 0}, // RBIT
{0, 1}, // REV16
{0, 2}, // REV32
@ -107,7 +107,7 @@ const u32 Data1SrcEnc[][2] = {
};
// Data-Processing (2 source)
const u32 Data2SrcEnc[] = {
static const u32 Data2SrcEnc[] = {
0x02, // UDIV
0x03, // SDIV
0x08, // LSLV
@ -125,7 +125,7 @@ const u32 Data2SrcEnc[] = {
};
// Data-Processing (3 source)
const u32 Data3SrcEnc[][2] = {
static const u32 Data3SrcEnc[][2] = {
{0, 0}, // MADD
{0, 1}, // MSUB
{1, 0}, // SMADDL (64Bit Only)
@ -137,7 +137,7 @@ const u32 Data3SrcEnc[][2] = {
};
// Logical (shifted register)
const u32 LogicalEnc[][2] = {
static const u32 LogicalEnc[][2] = {
{0, 0}, // AND
{0, 1}, // BIC
{1, 0}, // OOR
@ -149,7 +149,7 @@ const u32 LogicalEnc[][2] = {
};
// Load/Store Exclusive
u32 LoadStoreExcEnc[][5] = {
static u32 LoadStoreExcEnc[][5] = {
{0, 0, 0, 0, 0}, // STXRB
{0, 0, 0, 0, 1}, // STLXRB
{0, 0, 1, 0, 0}, // LDXRB

14
Source/Core/Common/ArmEmitter.cpp
View File

@ -543,7 +543,8 @@ void ARMXEmitter::WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg
// IMM, REG, IMMSREG, RSR
// -1 for invalid if the instruction doesn't support that
const s32 InstOps[][4] = {{16, 0, 0, 0}, // AND(s)
static const s32 InstOps[][4] = {
{16, 0, 0, 0}, // AND(s)
{17, 1, 1, 1}, // EOR(s)
{18, 2, 2, 2}, // SUB(s)
{19, 3, 3, 3}, // RSB(s)
@ -561,9 +562,10 @@ const s32 InstOps[][4] = {{16, 0, 0, 0}, // AND(s)
{31, 15, 15, 15}, // MVN(s)
{24, -1, -1, -1}, // MOVW
{26, -1, -1, -1}, // MOVT
};
};
const char *InstNames[] = {"AND",
static const char* InstNames[] = {
"AND",
"EOR",
"SUB",
"RSB",
@ -579,7 +581,7 @@ const char *InstNames[] = {"AND",
"MOV",
"BIC",
"MVN"
};
};
void ARMXEmitter::AND (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(0, Rd, Rn, Rm); }
void ARMXEmitter::ANDS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(0, Rd, Rn, Rm, true); }
@ -774,7 +776,7 @@ void ARMXEmitter::SVC(Operand2 op)
// IMM, REG, IMMSREG, RSR
// -1 for invalid if the instruction doesn't support that
const s32 LoadStoreOps[][4] = {
static const s32 LoadStoreOps[][4] = {
{0x40, 0x60, 0x60, -1}, // STR
{0x41, 0x61, 0x61, -1}, // LDR
{0x44, 0x64, 0x64, -1}, // STRB
@ -785,7 +787,7 @@ const s32 LoadStoreOps[][4] = {
{ 0x5, 0x1, -1, -1}, // LDRSB
{ 0x5, 0x1, -1, -1}, // LDRSH
};
const char *LoadStoreNames[] = {
static const char* LoadStoreNames[] = {
"STR",
"LDR",
"STRB",