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Merge pull request #10064 from lioncash/regs
Gekko: Migrate register structs over to Common::BitField
This commit is contained in:
Léo Lam
GitHub
commit
271612f328
@ -350,16 +350,14 @@ union UGQR
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// XER
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// XER
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union UReg_XER
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union UReg_XER
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{
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{
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struct
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BitField<0, 7, u32> BYTE_COUNT;
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{
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BitField<7, 1, u32> reserved_1;
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u32 BYTE_COUNT : 7;
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BitField<8, 8, u32> BYTE_CMP;
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u32 : 1;
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BitField<16, 13, u32> reserved_2;
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u32 BYTE_CMP : 8;
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BitField<29, 1, u32> CA;
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u32 : 13;
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BitField<30, 1, u32> OV;
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u32 CA : 1;
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BitField<31, 1, u32> SO;
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u32 OV : 1;
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u32 SO : 1;
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};
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u32 Hex = 0;
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u32 Hex = 0;
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UReg_XER() = default;
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UReg_XER() = default;
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@ -369,29 +367,27 @@ union UReg_XER
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// Machine State Register
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// Machine State Register
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union UReg_MSR
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union UReg_MSR
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{
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{
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struct
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BitField<0, 1, u32> LE;
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{
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BitField<1, 1, u32> RI;
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u32 LE : 1;
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BitField<2, 1, u32> PM;
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u32 RI : 1;
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BitField<3, 1, u32> reserved_1;
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u32 PM : 1;
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BitField<4, 1, u32> DR;
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u32 : 1; // res28
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BitField<5, 1, u32> IR;
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u32 DR : 1;
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BitField<6, 1, u32> IP;
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u32 IR : 1;
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BitField<7, 1, u32> reserved_2;
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u32 IP : 1;
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BitField<8, 1, u32> FE1;
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u32 : 1; // res24
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BitField<9, 1, u32> BE;
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u32 FE1 : 1;
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BitField<10, 1, u32> SE;
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u32 BE : 1;
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BitField<11, 1, u32> FE0;
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u32 SE : 1;
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BitField<12, 1, u32> MCHECK;
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u32 FE0 : 1;
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BitField<13, 1, u32> FP;
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u32 MCHECK : 1;
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BitField<14, 1, u32> PR;
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u32 FP : 1;
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BitField<15, 1, u32> EE;
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u32 PR : 1;
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BitField<16, 1, u32> ILE;
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u32 EE : 1;
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BitField<17, 1, u32> reserved_3;
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u32 ILE : 1;
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BitField<18, 1, u32> POW;
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u32 : 1; // res14
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BitField<19, 13, u32> reserved_4;
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u32 POW : 1;
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u32 res : 13;
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};
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u32 Hex = 0;
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u32 Hex = 0;
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UReg_MSR() = default;
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UReg_MSR() = default;
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@ -433,64 +429,62 @@ enum FPSCRExceptionFlag : u32
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// Floating Point Status and Control Register
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// Floating Point Status and Control Register
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union UReg_FPSCR
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union UReg_FPSCR
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{
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{
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struct
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// Rounding mode (towards: nearest, zero, +inf, -inf)
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{
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BitField<0, 2, FPURoundMode::RoundMode> RN;
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// Rounding mode (towards: nearest, zero, +inf, -inf)
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// Non-IEEE mode enable (aka flush-to-zero)
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FPURoundMode::RoundMode RN : 2;
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BitField<2, 1, u32> NI;
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// Non-IEEE mode enable (aka flush-to-zero)
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// Inexact exception enable
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u32 NI : 1;
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BitField<3, 1, u32> XE;
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// Inexact exception enable
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// IEEE division by zero exception enable
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u32 XE : 1;
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BitField<4, 1, u32> ZE;
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// IEEE division by zero exception enable
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// IEEE underflow exception enable
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u32 ZE : 1;
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BitField<5, 1, u32> UE;
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// IEEE underflow exception enable
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// IEEE overflow exception enable
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u32 UE : 1;
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BitField<6, 1, u32> OE;
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// IEEE overflow exception enable
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// Invalid operation exception enable
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u32 OE : 1;
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BitField<7, 1, u32> VE;
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// Invalid operation exception enable
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// Invalid operation exception for integer conversion (sticky)
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u32 VE : 1;
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BitField<8, 1, u32> VXCVI;
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// Invalid operation exception for integer conversion (sticky)
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// Invalid operation exception for square root (sticky)
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u32 VXCVI : 1;
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BitField<9, 1, u32> VXSQRT;
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// Invalid operation exception for square root (sticky)
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// Invalid operation exception for software request (sticky)
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u32 VXSQRT : 1;
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BitField<10, 1, u32> VXSOFT;
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// Invalid operation exception for software request (sticky)
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// reserved
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u32 VXSOFT : 1;
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BitField<11, 1, u32> reserved;
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// reserved
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// Floating point result flags (includes FPCC) (not sticky)
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u32 : 1;
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// from more to less significand: class, <, >, =, ?
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// Floating point result flags (includes FPCC) (not sticky)
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BitField<12, 5, u32> FPRF;
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// from more to less significand: class, <, >, =, ?
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// Fraction inexact (not sticky)
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u32 FPRF : 5;
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BitField<17, 1, u32> FI;
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// Fraction inexact (not sticky)
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// Fraction rounded (not sticky)
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u32 FI : 1;
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BitField<18, 1, u32> FR;
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// Fraction rounded (not sticky)
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// Invalid operation exception for invalid comparison (sticky)
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u32 FR : 1;
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BitField<19, 1, u32> VXVC;
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// Invalid operation exception for invalid comparison (sticky)
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// Invalid operation exception for inf * 0 (sticky)
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u32 VXVC : 1;
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BitField<20, 1, u32> VXIMZ;
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// Invalid operation exception for inf * 0 (sticky)
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// Invalid operation exception for 0 / 0 (sticky)
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u32 VXIMZ : 1;
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BitField<21, 1, u32> VXZDZ;
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// Invalid operation exception for 0 / 0 (sticky)
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// Invalid operation exception for inf / inf (sticky)
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u32 VXZDZ : 1;
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BitField<22, 1, u32> VXIDI;
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// Invalid operation exception for inf / inf (sticky)
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// Invalid operation exception for inf - inf (sticky)
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u32 VXIDI : 1;
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BitField<23, 1, u32> VXISI;
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// Invalid operation exception for inf - inf (sticky)
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// Invalid operation exception for SNaN (sticky)
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u32 VXISI : 1;
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BitField<24, 1, u32> VXSNAN;
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// Invalid operation exception for SNaN (sticky)
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// Inexact exception (sticky)
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u32 VXSNAN : 1;
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BitField<25, 1, u32> XX;
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// Inexact exception (sticky)
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// Division by zero exception (sticky)
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u32 XX : 1;
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BitField<26, 1, u32> ZX;
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// Division by zero exception (sticky)
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// Underflow exception (sticky)
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u32 ZX : 1;
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BitField<27, 1, u32> UX;
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// Underflow exception (sticky)
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// Overflow exception (sticky)
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u32 UX : 1;
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BitField<28, 1, u32> OX;
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// Overflow exception (sticky)
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// Invalid operation exception summary (not sticky)
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u32 OX : 1;
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BitField<29, 1, u32> VX;
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// Invalid operation exception summary (not sticky)
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// Enabled exception summary (not sticky)
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u32 VX : 1;
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BitField<30, 1, u32> FEX;
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// Enabled exception summary (not sticky)
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// Exception summary (sticky)
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u32 FEX : 1;
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BitField<31, 1, u32> FX;
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// Exception summary (sticky)
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u32 FX : 1;
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};
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u32 Hex = 0;
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u32 Hex = 0;
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// The FPSCR's 20th bit (11th from a little endian perspective)
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// The FPSCR's 20th bit (11th from a little endian perspective)
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@ -535,62 +529,58 @@ union UReg_FPSCR
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// Hardware Implementation-Dependent Register 0
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// Hardware Implementation-Dependent Register 0
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union UReg_HID0
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union UReg_HID0
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{
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{
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struct
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BitField<0, 1, u32> NOOPTI;
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{
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BitField<1, 1, u32> reserved_1;
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u32 NOOPTI : 1;
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BitField<2, 1, u32> BHT;
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u32 : 1;
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BitField<3, 1, u32> ABE;
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u32 BHT : 1;
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BitField<4, 1, u32> reserved_2;
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u32 ABE : 1;
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BitField<5, 1, u32> BTIC;
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u32 : 1;
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BitField<6, 1, u32> DCFA;
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u32 BTIC : 1;
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BitField<7, 1, u32> SGE;
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u32 DCFA : 1;
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BitField<8, 1, u32> IFEM;
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u32 SGE : 1;
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BitField<9, 1, u32> SPD;
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u32 IFEM : 1;
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BitField<10, 1, u32> DCFI;
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u32 SPD : 1;
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BitField<11, 1, u32> ICFI;
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u32 DCFI : 1;
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BitField<12, 1, u32> DLOCK;
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u32 ICFI : 1;
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BitField<13, 1, u32> ILOCK;
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u32 DLOCK : 1;
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BitField<14, 1, u32> DCE;
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u32 ILOCK : 1;
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BitField<15, 1, u32> ICE;
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u32 DCE : 1;
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BitField<16, 1, u32> NHR;
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u32 ICE : 1;
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BitField<17, 3, u32> reserved_3;
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u32 NHR : 1;
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BitField<20, 1, u32> DPM;
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u32 : 3;
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BitField<21, 1, u32> SLEEP;
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u32 DPM : 1;
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BitField<22, 1, u32> NAP;
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u32 SLEEP : 1;
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BitField<23, 1, u32> DOZE;
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u32 NAP : 1;
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BitField<24, 1, u32> PAR;
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u32 DOZE : 1;
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BitField<25, 1, u32> ECLK;
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u32 PAR : 1;
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BitField<26, 1, u32> reserved_4;
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u32 ECLK : 1;
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BitField<27, 1, u32> BCLK;
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u32 : 1;
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BitField<28, 1, u32> EBD;
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u32 BCLK : 1;
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BitField<29, 1, u32> EBA;
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u32 EBD : 1;
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BitField<30, 1, u32> DBP;
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u32 EBA : 1;
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BitField<31, 1, u32> EMCP;
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u32 DBP : 1;
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u32 EMCP : 1;
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};
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u32 Hex = 0;
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u32 Hex = 0;
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};
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};
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// Hardware Implementation-Dependent Register 2
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// Hardware Implementation-Dependent Register 2
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union UReg_HID2
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union UReg_HID2
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{
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{
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struct
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BitField<0, 16, u32> reserved;
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{
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BitField<16, 1, u32> DQOEE;
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u32 : 16;
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BitField<17, 1, u32> DCMEE;
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u32 DQOEE : 1;
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BitField<18, 1, u32> DNCEE;
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u32 DCMEE : 1;
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BitField<19, 1, u32> DCHEE;
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u32 DNCEE : 1;
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BitField<20, 1, u32> DQOERR;
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u32 DCHEE : 1;
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BitField<21, 1, u32> DCMERR;
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u32 DQOERR : 1;
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BitField<22, 1, u32> DNCERR;
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u32 DCMERR : 1;
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BitField<23, 1, u32> DCHERR;
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u32 DNCERR : 1;
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BitField<24, 4, u32> DMAQL;
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u32 DCHERR : 1;
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BitField<28, 1, u32> LCE;
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u32 DMAQL : 4;
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BitField<29, 1, u32> PSE;
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u32 LCE : 1;
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BitField<30, 1, u32> WPE;
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u32 PSE : 1;
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BitField<31, 1, u32> LSQE;
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u32 WPE : 1;
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u32 LSQE : 1;
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};
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u32 Hex = 0;
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u32 Hex = 0;
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UReg_HID2() = default;
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UReg_HID2() = default;
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@ -600,83 +590,73 @@ union UReg_HID2
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// Hardware Implementation-Dependent Register 4
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// Hardware Implementation-Dependent Register 4
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union UReg_HID4
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union UReg_HID4
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{
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{
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struct
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BitField<0, 20, u32> reserved_1;
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{
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BitField<20, 1, u32> L2CFI;
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u32 : 20;
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BitField<21, 1, u32> L2MUM;
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u32 L2CFI : 1;
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BitField<22, 1, u32> DBP;
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u32 L2MUM : 1;
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BitField<23, 1, u32> LPE;
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u32 DBP : 1;
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BitField<24, 1, u32> ST0;
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u32 LPE : 1;
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BitField<25, 1, u32> SBE;
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u32 ST0 : 1;
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BitField<26, 1, u32> reserved_2;
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u32 SBE : 1;
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BitField<27, 2, u32> BPD;
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u32 : 1;
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BitField<29, 2, u32> L2FM;
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u32 BPD : 2;
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BitField<31, 1, u32> reserved_3;
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u32 L2FM : 2;
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u32 : 1;
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};
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u32 Hex = 0;
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u32 Hex = 0;
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UReg_HID4() = default;
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UReg_HID4() = default;
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explicit UReg_HID4(u32 hex_) : Hex{hex_} {}
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explicit UReg_HID4(u32 hex_) : Hex{hex_} {}
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};
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};
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// SPR1 - Page Table format
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// SDR1 - Page Table format
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union UReg_SPR1
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union UReg_SDR1
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{
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{
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u32 Hex;
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BitField<0, 16, u32> htaborg;
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struct
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BitField<16, 7, u32> reserved;
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{
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BitField<23, 9, u32> htabmask;
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u32 htaborg : 16;
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u32 : 7;
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u32 Hex = 0;
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u32 htabmask : 9;
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};
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};
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};
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// MMCR0 - Monitor Mode Control Register 0 format
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// MMCR0 - Monitor Mode Control Register 0 format
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union UReg_MMCR0
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union UReg_MMCR0
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{
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{
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u32 Hex;
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BitField<0, 6, u32> PMC2SELECT;
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struct
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BitField<6, 7, u32> PMC1SELECT;
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{
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BitField<13, 1, u32> PMCTRIGGER;
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u32 PMC2SELECT : 6;
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BitField<14, 1, u32> PMCINTCONTROL;
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u32 PMC1SELECT : 7;
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BitField<15, 1, u32> PMC1INTCONTROL;
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u32 PMCTRIGGER : 1;
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BitField<16, 6, u32> THRESHOLD;
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u32 PMCINTCONTROL : 1;
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BitField<22, 1, u32> INTONBITTRANS;
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u32 PMC1INTCONTROL : 1;
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BitField<23, 2, u32> RTCSELECT;
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u32 THRESHOLD : 6;
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BitField<25, 1, u32> DISCOUNT;
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u32 INTONBITTRANS : 1;
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BitField<26, 1, u32> ENINT;
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u32 RTCSELECT : 2;
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BitField<27, 1, u32> DMR;
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u32 DISCOUNT : 1;
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BitField<28, 1, u32> DMS;
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u32 ENINT : 1;
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BitField<29, 1, u32> DU;
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u32 DMR : 1;
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BitField<30, 1, u32> DP;
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u32 DMS : 1;
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BitField<31, 1, u32> DIS;
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u32 DU : 1;
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u32 DP : 1;
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u32 Hex = 0;
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u32 DIS : 1;
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};
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};
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};
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// MMCR1 - Monitor Mode Control Register 1 format
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// MMCR1 - Monitor Mode Control Register 1 format
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union UReg_MMCR1
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union UReg_MMCR1
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{
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{
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u32 Hex;
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BitField<0, 22, u32> reserved;
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struct
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BitField<22, 5, u32> PMC4SELECT;
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{
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BitField<27, 5, u32> PMC3SELECT;
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u32 : 22;
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u32 PMC4SELECT : 5;
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u32 Hex = 0;
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u32 PMC3SELECT : 5;
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};
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};
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};
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// Write Pipe Address Register
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// Write Pipe Address Register
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union UReg_WPAR
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union UReg_WPAR
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{
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{
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struct
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BitField<0, 1, u32> BNE;
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{
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BitField<1, 4, u32> reserved;
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u32 BNE : 1;
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BitField<5, 27, u32> GB_ADDR;
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u32 : 4;
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u32 GB_ADDR : 27;
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};
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u32 Hex = 0;
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u32 Hex = 0;
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UReg_WPAR() = default;
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UReg_WPAR() = default;
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@ -686,11 +666,9 @@ union UReg_WPAR
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// Direct Memory Access Upper register
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// Direct Memory Access Upper register
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union UReg_DMAU
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union UReg_DMAU
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{
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{
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struct
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BitField<0, 5, u32> DMA_LEN_U;
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{
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BitField<5, 27, u32> MEM_ADDR;
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u32 DMA_LEN_U : 5;
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u32 MEM_ADDR : 27;
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};
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u32 Hex = 0;
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u32 Hex = 0;
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UReg_DMAU() = default;
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UReg_DMAU() = default;
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@ -700,14 +678,12 @@ union UReg_DMAU
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// Direct Memory Access Lower (DMAL) register
|
// Direct Memory Access Lower (DMAL) register
|
||||||
union UReg_DMAL
|
union UReg_DMAL
|
||||||
{
|
{
|
||||||
struct
|
BitField<0, 1, u32> DMA_F;
|
||||||
{
|
BitField<1, 1, u32> DMA_T;
|
||||||
u32 DMA_F : 1;
|
BitField<2, 2, u32> DMA_LEN_L;
|
||||||
u32 DMA_T : 1;
|
BitField<4, 1, u32> DMA_LD;
|
||||||
u32 DMA_LEN_L : 2;
|
BitField<5, 27, u32> LC_ADDR;
|
||||||
u32 DMA_LD : 1;
|
|
||||||
u32 LC_ADDR : 27;
|
|
||||||
};
|
|
||||||
u32 Hex = 0;
|
u32 Hex = 0;
|
||||||
|
|
||||||
UReg_DMAL() = default;
|
UReg_DMAL() = default;
|
||||||
@ -716,14 +692,12 @@ union UReg_DMAL
|
|||||||
|
|
||||||
union UReg_BAT_Up
|
union UReg_BAT_Up
|
||||||
{
|
{
|
||||||
struct
|
BitField<0, 1, u32> VP;
|
||||||
{
|
BitField<1, 1, u32> VS;
|
||||||
u32 VP : 1;
|
BitField<2, 11, u32> BL; // Block length (aka block size mask)
|
||||||
u32 VS : 1;
|
BitField<13, 4, u32> reserved;
|
||||||
u32 BL : 11; // Block length (aka block size mask)
|
BitField<17, 15, u32> BEPI;
|
||||||
u32 : 4;
|
|
||||||
u32 BEPI : 15;
|
|
||||||
};
|
|
||||||
u32 Hex = 0;
|
u32 Hex = 0;
|
||||||
|
|
||||||
UReg_BAT_Up() = default;
|
UReg_BAT_Up() = default;
|
||||||
@ -732,14 +706,12 @@ union UReg_BAT_Up
|
|||||||
|
|
||||||
union UReg_BAT_Lo
|
union UReg_BAT_Lo
|
||||||
{
|
{
|
||||||
struct
|
BitField<0, 2, u32> PP;
|
||||||
{
|
BitField<2, 1, u32> reserved_1;
|
||||||
u32 PP : 2;
|
BitField<3, 4, u32> WIMG;
|
||||||
u32 : 1;
|
BitField<7, 10, u32> reserved_2;
|
||||||
u32 WIMG : 4;
|
BitField<17, 15, u32> BRPN; // Physical Block Number
|
||||||
u32 : 10;
|
|
||||||
u32 BRPN : 15; // Physical Block Number
|
|
||||||
};
|
|
||||||
u32 Hex = 0;
|
u32 Hex = 0;
|
||||||
|
|
||||||
UReg_BAT_Lo() = default;
|
UReg_BAT_Lo() = default;
|
||||||
@ -748,16 +720,14 @@ union UReg_BAT_Lo
|
|||||||
|
|
||||||
union UReg_THRM12
|
union UReg_THRM12
|
||||||
{
|
{
|
||||||
struct
|
BitField<0, 1, u32> V; // Valid
|
||||||
{
|
BitField<1, 1, u32> TIE; // Thermal Interrupt Enable
|
||||||
u32 V : 1; // Valid
|
BitField<2, 1, u32> TID; // Thermal Interrupt Direction
|
||||||
u32 TIE : 1; // Thermal Interrupt Enable
|
BitField<3, 20, u32> reserved;
|
||||||
u32 TID : 1; // Thermal Interrupt Direction
|
BitField<23, 7, u32> THRESHOLD; // Temperature Threshold, 0-127°C
|
||||||
u32 : 20;
|
BitField<30, 1, u32> TIV; // Thermal Interrupt Valid
|
||||||
u32 THRESHOLD : 7; // Temperature Threshold, 0-127°C
|
BitField<31, 1, u32> TIN; // Thermal Interrupt
|
||||||
u32 TIV : 1; // Thermal Interrupt Valid
|
|
||||||
u32 TIN : 1; // Thermal Interrupt
|
|
||||||
};
|
|
||||||
u32 Hex = 0;
|
u32 Hex = 0;
|
||||||
|
|
||||||
UReg_THRM12() = default;
|
UReg_THRM12() = default;
|
||||||
@ -766,12 +736,10 @@ union UReg_THRM12
|
|||||||
|
|
||||||
union UReg_THRM3
|
union UReg_THRM3
|
||||||
{
|
{
|
||||||
struct
|
BitField<0, 1, u32> E; // Enable
|
||||||
{
|
BitField<1, 13, u32> SITV; // Sample Interval Timer Value
|
||||||
u32 E : 1; // Enable
|
BitField<14, 18, u32> reserved;
|
||||||
u32 SITV : 13; // Sample Interval Timer Value
|
|
||||||
u32 : 18;
|
|
||||||
};
|
|
||||||
u32 Hex = 0;
|
u32 Hex = 0;
|
||||||
|
|
||||||
UReg_THRM3() = default;
|
UReg_THRM3() = default;
|
||||||
@ -780,20 +748,17 @@ union UReg_THRM3
|
|||||||
|
|
||||||
union UReg_PTE
|
union UReg_PTE
|
||||||
{
|
{
|
||||||
struct
|
BitField<0, 6, u64> API;
|
||||||
{
|
BitField<6, 1, u64> H;
|
||||||
u64 API : 6;
|
BitField<7, 24, u64> VSID;
|
||||||
u64 H : 1;
|
BitField<31, 1, u64> V;
|
||||||
u64 VSID : 24;
|
BitField<32, 2, u64> PP;
|
||||||
u64 V : 1;
|
BitField<34, 1, u64> reserved_1;
|
||||||
u64 PP : 2;
|
BitField<35, 4, u64> WIMG;
|
||||||
u64 : 1;
|
BitField<39, 1, u64> C;
|
||||||
u64 WIMG : 4;
|
BitField<40, 1, u64> R;
|
||||||
u64 C : 1;
|
BitField<41, 3, u64> reserved_2;
|
||||||
u64 R : 1;
|
BitField<44, 20, u64> RPN;
|
||||||
u64 : 3;
|
|
||||||
u64 RPN : 20;
|
|
||||||
};
|
|
||||||
|
|
||||||
u64 Hex = 0;
|
u64 Hex = 0;
|
||||||
u32 Hex32[2];
|
u32 Hex32[2];
|
||||||
|
|||||||
@ -226,7 +226,7 @@ void Interpreter::fcmpu(UGeckoInstruction inst)
|
|||||||
|
|
||||||
void Interpreter::fctiwx(UGeckoInstruction inst)
|
void Interpreter::fctiwx(UGeckoInstruction inst)
|
||||||
{
|
{
|
||||||
ConvertToInteger(inst, static_cast<RoundingMode>(FPSCR.RN));
|
ConvertToInteger(inst, static_cast<RoundingMode>(FPSCR.RN.Value()));
|
||||||
}
|
}
|
||||||
|
|
||||||
void Interpreter::fctiwzx(UGeckoInstruction inst)
|
void Interpreter::fctiwzx(UGeckoInstruction inst)
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user