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[ARM] Support both hardfp and softfp with lfs and lfd. Fixes these two instructions on Android since it uses softfp calling conventions. This adds a emitter for moving from two ARM Registers to a double VFP reg.

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This commit is contained in:
Ryan Houdek 2013-08-30 09:37:57 +00:00
parent 2ab7fc10da
commit 2c1337eb5f
2 changed files with 12 additions and 2 deletions
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5
Source/Core/Common/Src/ArmEmitter.cpp
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@ -1154,7 +1154,10 @@ void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src)
else else
{ {
// Move 64bit from Arm reg // Move 64bit from Arm reg
_dbg_assert_msg_(DYNA_REC, false, "This VMOV doesn't support moving 64bit ARM to NEON"); ARMReg Src2 = (ARMReg)(Src + 1);
Dest = (ARMReg)(Dest - S0);
Write32(condition | (0xC4 << 20) | (Src2 << 16) | (Src << 12) \
| (0xB << 8) | ((Dest & 0x10) << 1) | (1 << 4) | ((Dest & 0xF) >> 1));
return; return;
} }
} }

9
Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp
View File

@ -61,6 +61,9 @@ void JitArm::lfs(UGeckoInstruction inst)
ARMReg v0 = fpr.R0(inst.FD); ARMReg v0 = fpr.R0(inst.FD);
ARMReg v1 = fpr.R1(inst.FD); ARMReg v1 = fpr.R1(inst.FD);
#if !defined(__ARM_PCS_VFP) // SoftFP returns in R0
VMOV(S0, R0);
#endif
VCVT(v0, S0, 0); VCVT(v0, S0, 0);
VCVT(v1, S0, 0); VCVT(v1, S0, 0);
@ -98,8 +101,12 @@ void JitArm::lfd(UGeckoInstruction inst)
BL(rA); BL(rA);
ARMReg v0 = fpr.R0(inst.FD); ARMReg v0 = fpr.R0(inst.FD);
#if !defined(__ARM_PCS_VFP) // SoftFP returns in R0 and R1
VMOV(v0, R0);
#else
VMOV(v0, D0); VMOV(v0, D0);
#endif
POP(4, R0, R1, R2, R3); POP(4, R0, R1, R2, R3);
gpr.Unlock(rA, rB); gpr.Unlock(rA, rB);