[maintenance] Add a note explaining why we aren't emulating CP clear register writes.

For further reference, see also r700f5eabc752.
This commit is contained in:
NeoBrainX 2012-01-21 14:58:29 +01:00
parent 96d56cd8ef
commit 2d6d73df95
2 changed files with 9 additions and 5 deletions

View File

@ -311,6 +311,7 @@ void Write16(const u16 _Value, const u32 _Address)
UCPClearReg tmpCtrl(_Value); UCPClearReg tmpCtrl(_Value);
m_CPClearReg.Hex = tmpCtrl.Hex; m_CPClearReg.Hex = tmpCtrl.Hex;
DEBUG_LOG(COMMANDPROCESSOR,"\t write to CLEAR_REGISTER : %04x", _Value); DEBUG_LOG(COMMANDPROCESSOR,"\t write to CLEAR_REGISTER : %04x", _Value);
SetCpClearRegister();
} }
break; break;
@ -677,13 +678,15 @@ void SetCpControlRegister()
} }
// NOTE: The implementation of this function should be correct, but we intentionally aren't using it at the moment.
// We don't emulate proper GP timing anyway at the moment, so this code would just slow down emulation.
void SetCpClearRegister() void SetCpClearRegister()
{ {
if (IsOnThread()) // if (IsOnThread())
{ // {
if (!m_CPClearReg.ClearFifoUnderflow && m_CPClearReg.ClearFifoOverflow) // if (!m_CPClearReg.ClearFifoUnderflow && m_CPClearReg.ClearFifoOverflow)
bProcessFifoToLoWatermark = true; // bProcessFifoToLoWatermark = true;
} // }
} }
} // end of namespace CommandProcessor } // end of namespace CommandProcessor

View File

@ -158,6 +158,7 @@ void UpdateInterruptsFromVideoBackend(u64 userdata);
bool AllowIdleSkipping(); bool AllowIdleSkipping();
void SetCpClearRegister();
void SetCpControlRegister(); void SetCpControlRegister();
void SetCpStatusRegister(); void SetCpStatusRegister();
void SetOverflowStatusFromGatherPipe(); void SetOverflowStatusFromGatherPipe();