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https://github.com/dolphin-emu/dolphin.git
synced 2025-01-27 00:05:34 +01:00
Revert my dual-core fix for FifoPlayer. Apparently it breaks more than it fixes.
This reverts commit bab9b5d3ce14c5b9cb55bd34da4851672e287467.
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parent
01d393ed6c
commit
37af25e03d
@ -20,7 +20,6 @@
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#include "Common.h"
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#include "Common.h"
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#include "CoreTiming.h"
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#include "CoreTiming.h"
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#include "Thread.h"
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#include "HW/GPFifo.h"
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#include "HW/GPFifo.h"
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#include "HW/Memmap.h"
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#include "HW/Memmap.h"
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@ -28,7 +27,6 @@
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#include "PowerPC/PowerPC.h"
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#include "PowerPC/PowerPC.h"
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#include "BPMemory.h"
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#include "BPMemory.h"
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#include "CommandProcessor.h"
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FifoPlayer::~FifoPlayer()
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FifoPlayer::~FifoPlayer()
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{
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{
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@ -96,41 +94,8 @@ bool FifoPlayer::Play()
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if (m_EarlyMemoryUpdates && m_CurrentFrame == m_FrameRangeStart)
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if (m_EarlyMemoryUpdates && m_CurrentFrame == m_FrameRangeStart)
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WriteAllMemoryUpdates();
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WriteAllMemoryUpdates();
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// Stop Fifo processing until we've written the new frame
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WriteCP(CommandProcessor::CTRL_REGISTER, 0x10); // disable read & breakpoints, enable GP link
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// Write frame data
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WriteFrame(m_File->GetFrame(m_CurrentFrame), m_FrameInfo[m_CurrentFrame]);
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WriteFrame(m_File->GetFrame(m_CurrentFrame), m_FrameInfo[m_CurrentFrame]);
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// Enable frame processing and break when done
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u16 write_ptr_lo = ReadCP(CommandProcessor::FIFO_WRITE_POINTER_LO);
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u16 write_ptr_hi = ReadCP(CommandProcessor::FIFO_WRITE_POINTER_HI);
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WriteCP(CommandProcessor::FIFO_BP_LO, write_ptr_lo);
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WriteCP(CommandProcessor::FIFO_BP_HI, write_ptr_hi);
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WriteCP(CommandProcessor::CTRL_REGISTER, 0x13); // enable read, breakpoints & GP link
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// If necessary, wait until GP has reached the breakpoint to prevent fifo overflows
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// TODO: Can this be done any better? Dual core mode is slower than single core mode even with these conditions..
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if (m_CurrentFrame < m_FrameRangeEnd)
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{
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// Check if FIFO would be overflown when writing the next frame
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u32 CPRWDistance = (ReadCP(CommandProcessor::FIFO_RW_DISTANCE_HI)<<16) | ReadCP(CommandProcessor::FIFO_RW_DISTANCE_LO);
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CPRWDistance += m_File->GetFrame(m_CurrentFrame+1).fifoDataSize + CommandProcessor::GATHER_PIPE_SIZE;
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u32 CPFifoBase = (ReadCP(CommandProcessor::FIFO_BASE_HI)<<16) | ReadCP(CommandProcessor::FIFO_BASE_LO);
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u32 CPFifoEnd = (ReadCP(CommandProcessor::FIFO_END_HI)<<16) | ReadCP(CommandProcessor::FIFO_END_LO);
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bool bWait = (CPRWDistance > CPFifoEnd - CPFifoBase);
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while (bWait && (ReadCP(CommandProcessor::FIFO_READ_POINTER_LO) != write_ptr_lo ||
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ReadCP(CommandProcessor::FIFO_READ_POINTER_HI) != write_ptr_hi))
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{
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Common::YieldCPU();
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CoreTiming::Advance(); // Process scheduled events (esp. PixelEngine::SetFinish!)
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if (PowerPC::GetState() == PowerPC::CPU_POWERDOWN)
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break;
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}
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}
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++m_CurrentFrame;
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++m_CurrentFrame;
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}
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}
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}
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}
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@ -422,11 +387,6 @@ void FifoPlayer::LoadMemory()
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FlushWGP();
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FlushWGP();
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}
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}
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u16 FifoPlayer::ReadCP(u32 address)
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{
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return Memory::Read_U16(0xCC000000 | address);
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}
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void FifoPlayer::WriteCP(u32 address, u16 value)
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void FifoPlayer::WriteCP(u32 address, u16 value)
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{
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{
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Memory::Write_U16(value, 0xCC000000 | address);
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Memory::Write_U16(value, 0xCC000000 | address);
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@ -87,7 +87,6 @@ private:
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void LoadMemory();
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void LoadMemory();
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u16 ReadCP(u32 address);
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void WriteCP(u32 address, u16 value);
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void WriteCP(u32 address, u16 value);
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void WritePI(u32 address, u32 value);
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void WritePI(u32 address, u32 value);
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