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Cleanup enum indentations.

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This commit is contained in:
Lioncash 2014-02-09 16:03:16 -05:00
parent e59f770ccb
commit 40182a48a5
65 changed files with 1031 additions and 1026 deletions
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12
Source/Core/Common/SymbolDB.h
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@ -56,12 +56,12 @@ struct Symbol
enum enum
{ {
FFLAG_TIMERINSTRUCTIONS=(1<<0), FFLAG_TIMERINSTRUCTIONS = (1<<0),
FFLAG_LEAF=(1<<1), FFLAG_LEAF = (1<<1),
FFLAG_ONLYCALLSNICELEAFS=(1<<2), FFLAG_ONLYCALLSNICELEAFS = (1<<2),
FFLAG_EVIL=(1<<3), FFLAG_EVIL = (1<<3),
FFLAG_RFI=(1<<4), FFLAG_RFI = (1<<4),
FFLAG_STRAIGHT=(1<<5) FFLAG_STRAIGHT = (1<<5)
}; };

6
Source/Core/Common/x64Emitter.h
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@ -43,10 +43,10 @@ enum CCFlags
{ {
CC_O = 0, CC_O = 0,
CC_NO = 1, CC_NO = 1,
CC_B = 2, CC_C = 2, CC_NAE = 2, CC_B = 2, CC_C = 2, CC_NAE = 2,
CC_NB = 3, CC_NC = 3, CC_AE = 3, CC_NB = 3, CC_NC = 3, CC_AE = 3,
CC_Z = 4, CC_E = 4, CC_Z = 4, CC_E = 4,
CC_NZ = 5, CC_NE = 5, CC_NZ = 5, CC_NE = 5,
CC_BE = 6, CC_NA = 6, CC_BE = 6, CC_NA = 6,
CC_NBE = 7, CC_A = 7, CC_NBE = 7, CC_A = 7,
CC_S = 8, CC_S = 8,

8
Source/Core/Core/Boot/Boot_DOL.h
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@ -14,8 +14,8 @@ public:
CDolLoader(u8* _pBuffer, u32 _Size); CDolLoader(u8* _pBuffer, u32 _Size);
~CDolLoader(); ~CDolLoader();
bool IsWii() { return m_isWii; } bool IsWii() { return m_isWii; }
u32 GetEntryPoint() { return m_dolheader.entryPoint; } u32 GetEntryPoint() { return m_dolheader.entryPoint; }
// Load into emulated memory // Load into emulated memory
void Load(); void Load();
@ -23,8 +23,8 @@ public:
private: private:
enum enum
{ {
DOL_NUM_TEXT = 7, DOL_NUM_TEXT = 7,
DOL_NUM_DATA = 11 DOL_NUM_DATA = 11
}; };
struct SDolHeader struct SDolHeader

4
Source/Core/Core/Boot/ElfReader.h
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@ -10,9 +10,9 @@
enum KnownElfTypes enum KnownElfTypes
{ {
KNOWNELF_PSP = 0, KNOWNELF_PSP = 0,
KNOWNELF_DS = 1, KNOWNELF_DS = 1,
KNOWNELF_GBA = 2, KNOWNELF_GBA = 2,
KNOWNELF_GC = 3, KNOWNELF_GC = 3,
}; };
typedef int SectionID; typedef int SectionID;

38
Source/Core/Core/Boot/ElfTypes.h
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@ -10,26 +10,26 @@
// File type // File type
enum ElfType enum ElfType
{ {
ET_NONE =0, ET_NONE = 0,
ET_REL =1, ET_REL = 1,
ET_EXEC =2, ET_EXEC = 2,
ET_DYN =3, ET_DYN = 3,
ET_CORE =4, ET_CORE = 4,
ET_LOPROC =0xFF00, ET_LOPROC = 0xFF00,
ET_HIPROC =0xFFFF, ET_HIPROC = 0xFFFF,
}; };
// Machine/Architecture // Machine/Architecture
enum ElfMachine enum ElfMachine
{ {
EM_NONE =0, EM_NONE = 0,
EM_M32 =1, EM_M32 = 1,
EM_SPARC =2, EM_SPARC = 2,
EM_386 =3, EM_386 = 3,
EM_68K =4, EM_68K = 4,
EM_88K =5, EM_88K = 5,
EM_860 =7, EM_860 = 7,
EM_MIPS =8 EM_MIPS = 8
}; };
// File version // File version
@ -101,10 +101,10 @@ enum ElfMachine
// Section flags // Section flags
enum ElfSectionFlags enum ElfSectionFlags
{ {
SHF_WRITE =0x1, SHF_WRITE = 0x1,
SHF_ALLOC =0x2, SHF_ALLOC = 0x2,
SHF_EXECINSTR =0x4, SHF_EXECINSTR = 0x4,
SHF_MASKPROC =0xF0000000, SHF_MASKPROC = 0xF0000000,
}; };
// Symbol binding // Symbol binding

10
Source/Core/Core/DSP/DSPAnalyzer.h
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@ -17,11 +17,11 @@ namespace DSPAnalyzer {
enum enum
{ {
CODE_START_OF_INST = 1, CODE_START_OF_INST = 1,
CODE_IDLE_SKIP = 2, CODE_IDLE_SKIP = 2,
CODE_LOOP_START = 4, CODE_LOOP_START = 4,
CODE_LOOP_END = 8, CODE_LOOP_END = 8,
CODE_UPDATE_SR = 16, CODE_UPDATE_SR = 16,
CODE_CHECK_INT = 32, CODE_CHECK_INT = 32,
}; };
// Easy to query array covering the whole of instruction memory. // Easy to query array covering the whole of instruction memory.

56
Source/Core/Core/DSP/DSPTables.h
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@ -20,37 +20,37 @@
enum partype_t enum partype_t
{ {
P_NONE = 0x0000, P_NONE = 0x0000,
P_VAL = 0x0001, P_VAL = 0x0001,
P_IMM = 0x0002, P_IMM = 0x0002,
P_MEM = 0x0003, P_MEM = 0x0003,
P_STR = 0x0004, P_STR = 0x0004,
P_ADDR_I = 0x0005, P_ADDR_I = 0x0005,
P_ADDR_D = 0x0006, P_ADDR_D = 0x0006,
P_REG = 0x8000, P_REG = 0x8000,
P_REG04 = P_REG | 0x0400, // IX P_REG04 = P_REG | 0x0400, // IX
P_REG08 = P_REG | 0x0800, P_REG08 = P_REG | 0x0800,
P_REG18 = P_REG | 0x1800, P_REG18 = P_REG | 0x1800,
P_REGM18 = P_REG | 0x1810, // used in multiply instructions P_REGM18 = P_REG | 0x1810, // used in multiply instructions
P_REG19 = P_REG | 0x1900, P_REG19 = P_REG | 0x1900,
P_REGM19 = P_REG | 0x1910, // used in multiply instructions P_REGM19 = P_REG | 0x1910, // used in multiply instructions
P_REG1A = P_REG | 0x1a80, P_REG1A = P_REG | 0x1a80,
P_REG1C = P_REG | 0x1c00, P_REG1C = P_REG | 0x1c00,
// P_ACC = P_REG | 0x1c10, // used for global accum (gcdsptool's value) // P_ACC = P_REG | 0x1c10, // used for global accum (gcdsptool's value)
P_ACCL = P_REG | 0x1c00, // used for low part of accum P_ACCL = P_REG | 0x1c00, // used for low part of accum
P_ACCM = P_REG | 0x1e00, // used for mid part of accum P_ACCM = P_REG | 0x1e00, // used for mid part of accum
// The following are not in gcdsptool // The following are not in gcdsptool
P_ACCM_D = P_REG | 0x1e80, P_ACCM_D = P_REG | 0x1e80,
P_ACC = P_REG | 0x2000, // used for full accum. P_ACC = P_REG | 0x2000, // used for full accum.
P_ACC_D = P_REG | 0x2080, P_ACC_D = P_REG | 0x2080,
P_AX = P_REG | 0x2200, P_AX = P_REG | 0x2200,
P_REGS_MASK = 0x03f80, // gcdsptool's value = 0x01f80 P_REGS_MASK = 0x03f80, // gcdsptool's value = 0x01f80
P_REF = P_REG | 0x4000, P_REF = P_REG | 0x4000,
P_PRG = P_REF | P_REG, P_PRG = P_REF | P_REG,
// The following seem like junk: // The following seem like junk:
// P_REG10 = P_REG | 0x1000, // P_REG10 = P_REG | 0x1000,
// P_AX_D = P_REG | 0x2280, // P_AX_D = P_REG | 0x2280,
}; };
#define OPTABLE_SIZE 0xffff + 1 #define OPTABLE_SIZE 0xffff + 1

6
Source/Core/Core/Debugger/Dump.h
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@ -25,9 +25,9 @@ public:
private: private:
enum enum
{ {
OFFSET_GPR = 0x4, OFFSET_GPR = 0x4,
OFFSET_PC = 0x194, OFFSET_PC = 0x194,
STRUCTUR_SIZE = 0x2BC STRUCTUR_SIZE = 0x2BC
}; };
u8 *m_pData; u8 *m_pData;

6
Source/Core/Core/FifoPlayer/FifoDataFile.h
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@ -17,10 +17,10 @@ struct MemoryUpdate
{ {
enum Type enum Type
{ {
TEXTURE_MAP = 0x01, TEXTURE_MAP = 0x01,
XF_DATA = 0x02, XF_DATA = 0x02,
VERTEX_STREAM = 0x04, VERTEX_STREAM = 0x04,
TMEM = 0x08, TMEM = 0x08,
}; };
u32 fifoPosition; u32 fifoPosition;

4
Source/Core/Core/FifoPlayer/FifoFileStruct.h
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@ -12,8 +12,8 @@ namespace FifoFileStruct
enum enum
{ {
FILE_ID = 0x0d01f1f0, FILE_ID = 0x0d01f1f0,
VERSION_NUMBER = 1, VERSION_NUMBER = 1,
MIN_LOADER_VERSION = 1, MIN_LOADER_VERSION = 1,
}; };

8
Source/Core/Core/HW/AudioInterface.cpp
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@ -69,10 +69,10 @@ namespace AudioInterface
// Internal hardware addresses // Internal hardware addresses
enum enum
{ {
AI_CONTROL_REGISTER = 0x6C00, AI_CONTROL_REGISTER = 0x6C00,
AI_VOLUME_REGISTER = 0x6C04, AI_VOLUME_REGISTER = 0x6C04,
AI_SAMPLE_COUNTER = 0x6C08, AI_SAMPLE_COUNTER = 0x6C08,
AI_INTERRUPT_TIMING = 0x6C0C, AI_INTERRUPT_TIMING = 0x6C0C,
}; };
enum enum

40
Source/Core/Core/HW/DSP.cpp
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@ -42,26 +42,26 @@ namespace DSP
// register offsets // register offsets
enum enum
{ {
DSP_MAIL_TO_DSP_HI = 0x5000, DSP_MAIL_TO_DSP_HI = 0x5000,
DSP_MAIL_TO_DSP_LO = 0x5002, DSP_MAIL_TO_DSP_LO = 0x5002,
DSP_MAIL_FROM_DSP_HI = 0x5004, DSP_MAIL_FROM_DSP_HI = 0x5004,
DSP_MAIL_FROM_DSP_LO = 0x5006, DSP_MAIL_FROM_DSP_LO = 0x5006,
DSP_CONTROL = 0x500A, DSP_CONTROL = 0x500A,
DSP_INTERRUPT_CONTROL = 0x5010, DSP_INTERRUPT_CONTROL = 0x5010,
AR_INFO = 0x5012, // These names are a good guess at best AR_INFO = 0x5012, // These names are a good guess at best
AR_MODE = 0x5016, // AR_MODE = 0x5016, //
AR_REFRESH = 0x501a, AR_REFRESH = 0x501a,
AR_DMA_MMADDR_H = 0x5020, AR_DMA_MMADDR_H = 0x5020,
AR_DMA_MMADDR_L = 0x5022, AR_DMA_MMADDR_L = 0x5022,
AR_DMA_ARADDR_H = 0x5024, AR_DMA_ARADDR_H = 0x5024,
AR_DMA_ARADDR_L = 0x5026, AR_DMA_ARADDR_L = 0x5026,
AR_DMA_CNT_H = 0x5028, AR_DMA_CNT_H = 0x5028,
AR_DMA_CNT_L = 0x502A, AR_DMA_CNT_L = 0x502A,
AUDIO_DMA_START_HI = 0x5030, AUDIO_DMA_START_HI = 0x5030,
AUDIO_DMA_START_LO = 0x5032, AUDIO_DMA_START_LO = 0x5032,
AUDIO_DMA_BLOCKS_LENGTH = 0x5034, // Ever used? AUDIO_DMA_BLOCKS_LENGTH = 0x5034, // Ever used?
AUDIO_DMA_CONTROL_LEN = 0x5036, AUDIO_DMA_CONTROL_LEN = 0x5036,
AUDIO_DMA_BLOCKS_LEFT = 0x503A, AUDIO_DMA_BLOCKS_LEFT = 0x503A,
}; };
// UARAMCount // UARAMCount

10
Source/Core/Core/HW/DSP.h
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@ -14,16 +14,16 @@ namespace DSP
enum DSPInterruptType enum DSPInterruptType
{ {
INT_DSP = 0, INT_DSP = 0,
INT_ARAM = 1, INT_ARAM = 1,
INT_AID = 2 INT_AID = 2
}; };
// aram size and mask // aram size and mask
enum enum
{ {
ARAM_SIZE = 0x01000000, // 16 MB ARAM_SIZE = 0x01000000, // 16 MB
ARAM_MASK = 0x00FFFFFF, ARAM_MASK = 0x00FFFFFF,
}; };
void Init(bool hle); void Init(bool hle);

96
Source/Core/Core/HW/DSPHLE/UCodes/UCode_AX.h
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@ -21,33 +21,33 @@
// mixer_control value to an AXMixControl bitfield. // mixer_control value to an AXMixControl bitfield.
enum AXMixControl enum AXMixControl
{ {
MIX_L = 0x000001, MIX_L = 0x000001,
MIX_L_RAMP = 0x000002, MIX_L_RAMP = 0x000002,
MIX_R = 0x000004, MIX_R = 0x000004,
MIX_R_RAMP = 0x000008, MIX_R_RAMP = 0x000008,
MIX_S = 0x000010, MIX_S = 0x000010,
MIX_S_RAMP = 0x000020, MIX_S_RAMP = 0x000020,
MIX_AUXA_L = 0x000040, MIX_AUXA_L = 0x000040,
MIX_AUXA_L_RAMP = 0x000080, MIX_AUXA_L_RAMP = 0x000080,
MIX_AUXA_R = 0x000100, MIX_AUXA_R = 0x000100,
MIX_AUXA_R_RAMP = 0x000200, MIX_AUXA_R_RAMP = 0x000200,
MIX_AUXA_S = 0x000400, MIX_AUXA_S = 0x000400,
MIX_AUXA_S_RAMP = 0x000800, MIX_AUXA_S_RAMP = 0x000800,
MIX_AUXB_L = 0x001000, MIX_AUXB_L = 0x001000,
MIX_AUXB_L_RAMP = 0x002000, MIX_AUXB_L_RAMP = 0x002000,
MIX_AUXB_R = 0x004000, MIX_AUXB_R = 0x004000,
MIX_AUXB_R_RAMP = 0x008000, MIX_AUXB_R_RAMP = 0x008000,
MIX_AUXB_S = 0x010000, MIX_AUXB_S = 0x010000,
MIX_AUXB_S_RAMP = 0x020000, MIX_AUXB_S_RAMP = 0x020000,
MIX_AUXC_L = 0x040000, MIX_AUXC_L = 0x040000,
MIX_AUXC_L_RAMP = 0x080000, MIX_AUXC_L_RAMP = 0x080000,
MIX_AUXC_R = 0x100000, MIX_AUXC_R = 0x100000,
MIX_AUXC_R_RAMP = 0x200000, MIX_AUXC_R_RAMP = 0x200000,
MIX_AUXC_S = 0x400000, MIX_AUXC_S = 0x400000,
MIX_AUXC_S_RAMP = 0x800000 MIX_AUXC_S_RAMP = 0x800000
}; };
class CUCode_AX : public IUCode class CUCode_AX : public IUCode
@ -69,13 +69,13 @@ public:
protected: protected:
enum MailType enum MailType
{ {
MAIL_RESUME = 0xCDD10000, MAIL_RESUME = 0xCDD10000,
MAIL_NEW_UCODE = 0xCDD10001, MAIL_NEW_UCODE = 0xCDD10001,
MAIL_RESET = 0xCDD10002, MAIL_RESET = 0xCDD10002,
MAIL_CONTINUE = 0xCDD10003, MAIL_CONTINUE = 0xCDD10003,
// CPU sends 0xBABE0000 | cmdlist_size to the DSP // CPU sends 0xBABE0000 | cmdlist_size to the DSP
MAIL_CMDLIST = 0xBABE0000, MAIL_CMDLIST = 0xBABE0000,
MAIL_CMDLIST_MASK = 0xFFFF0000 MAIL_CMDLIST_MASK = 0xFFFF0000
}; };
@ -157,26 +157,26 @@ protected:
private: private:
enum CmdType enum CmdType
{ {
CMD_SETUP = 0x00, CMD_SETUP = 0x00,
CMD_DL_AND_VOL_MIX = 0x01, CMD_DL_AND_VOL_MIX = 0x01,
CMD_PB_ADDR = 0x02, CMD_PB_ADDR = 0x02,
CMD_PROCESS = 0x03, CMD_PROCESS = 0x03,
CMD_MIX_AUXA = 0x04, CMD_MIX_AUXA = 0x04,
CMD_MIX_AUXB = 0x05, CMD_MIX_AUXB = 0x05,
CMD_UPLOAD_LRS = 0x06, CMD_UPLOAD_LRS = 0x06,
CMD_SET_LR = 0x07, CMD_SET_LR = 0x07,
CMD_UNK_08 = 0x08, CMD_UNK_08 = 0x08,
CMD_MIX_AUXB_NOWRITE = 0x09, CMD_MIX_AUXB_NOWRITE = 0x09,
CMD_COMPRESSOR_TABLE_ADDR = 0x0A, CMD_COMPRESSOR_TABLE_ADDR = 0x0A,
CMD_UNK_0B = 0x0B, CMD_UNK_0B = 0x0B,
CMD_UNK_0C = 0x0C, CMD_UNK_0C = 0x0C,
CMD_MORE = 0x0D, CMD_MORE = 0x0D,
CMD_OUTPUT = 0x0E, CMD_OUTPUT = 0x0E,
CMD_END = 0x0F, CMD_END = 0x0F,
CMD_MIX_AUXB_LR = 0x10, CMD_MIX_AUXB_LR = 0x10,
CMD_SET_OPPOSITE_LR = 0x11, CMD_SET_OPPOSITE_LR = 0x11,
CMD_UNK_12 = 0x12, CMD_UNK_12 = 0x12,
CMD_SEND_AUX_AND_MIX = 0x13, CMD_SEND_AUX_AND_MIX = 0x13,
}; };
}; };

54
Source/Core/Core/HW/DSPHLE/UCodes/UCode_AXWii.h
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@ -71,21 +71,21 @@ protected:
private: private:
enum CmdType enum CmdType
{ {
CMD_SETUP = 0x00, CMD_SETUP = 0x00,
CMD_ADD_TO_LR = 0x01, CMD_ADD_TO_LR = 0x01,
CMD_SUB_TO_LR = 0x02, CMD_SUB_TO_LR = 0x02,
CMD_ADD_SUB_TO_LR = 0x03, CMD_ADD_SUB_TO_LR = 0x03,
CMD_PROCESS = 0x04, CMD_PROCESS = 0x04,
CMD_MIX_AUXA = 0x05, CMD_MIX_AUXA = 0x05,
CMD_MIX_AUXB = 0x06, CMD_MIX_AUXB = 0x06,
CMD_MIX_AUXC = 0x07, CMD_MIX_AUXC = 0x07,
CMD_UPL_AUXA_MIX_LRSC = 0x08, CMD_UPL_AUXA_MIX_LRSC = 0x08,
CMD_UPL_AUXB_MIX_LRSC = 0x09, CMD_UPL_AUXB_MIX_LRSC = 0x09,
CMD_UNK_0A = 0x0A, CMD_UNK_0A = 0x0A,
CMD_OUTPUT = 0x0B, CMD_OUTPUT = 0x0B,
CMD_OUTPUT_DPL2 = 0x0C, CMD_OUTPUT_DPL2 = 0x0C,
CMD_WM_OUTPUT = 0x0D, CMD_WM_OUTPUT = 0x0D,
CMD_END = 0x0E, CMD_END = 0x0E,
}; };
// A lot of these are similar to the new version, but there is an offset in // A lot of these are similar to the new version, but there is an offset in
@ -93,22 +93,22 @@ private:
// new AXWii). // new AXWii).
enum CmdTypeOld enum CmdTypeOld
{ {
CMD_SETUP_OLD = 0x00, CMD_SETUP_OLD = 0x00,
CMD_ADD_TO_LR_OLD = 0x01, CMD_ADD_TO_LR_OLD = 0x01,
CMD_SUB_TO_LR_OLD = 0x02, CMD_SUB_TO_LR_OLD = 0x02,
CMD_ADD_SUB_TO_LR_OLD = 0x03, CMD_ADD_SUB_TO_LR_OLD = 0x03,
CMD_PB_ADDR_OLD = 0x04, CMD_PB_ADDR_OLD = 0x04,
CMD_PROCESS_OLD = 0x05, CMD_PROCESS_OLD = 0x05,
CMD_MIX_AUXA_OLD = 0x06, CMD_MIX_AUXA_OLD = 0x06,
CMD_MIX_AUXB_OLD = 0x07, CMD_MIX_AUXB_OLD = 0x07,
CMD_MIX_AUXC_OLD = 0x08, CMD_MIX_AUXC_OLD = 0x08,
CMD_UPL_AUXA_MIX_LRSC_OLD = 0x09, CMD_UPL_AUXA_MIX_LRSC_OLD = 0x09,
CMD_UPL_AUXB_MIX_LRSC_OLD = 0x0a, CMD_UPL_AUXB_MIX_LRSC_OLD = 0x0a,
CMD_UNK_0B_OLD = 0x0B, CMD_UNK_0B_OLD = 0x0B,
CMD_OUTPUT_OLD = 0x0C, // no volume! CMD_OUTPUT_OLD = 0x0C, // no volume!
CMD_OUTPUT_DPL2_OLD = 0x0D, CMD_OUTPUT_DPL2_OLD = 0x0D,
CMD_WM_OUTPUT_OLD = 0x0E, CMD_WM_OUTPUT_OLD = 0x0E,
CMD_END_OLD = 0x0F CMD_END_OLD = 0x0F
}; };
}; };

12
Source/Core/Core/HW/DSPHLE/UCodes/UCodes.h
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@ -100,12 +100,12 @@ protected:
enum EDSP_Codes enum EDSP_Codes
{ {
DSP_INIT = 0xDCD10000, DSP_INIT = 0xDCD10000,
DSP_RESUME = 0xDCD10001, DSP_RESUME = 0xDCD10001,
DSP_YIELD = 0xDCD10002, DSP_YIELD = 0xDCD10002,
DSP_DONE = 0xDCD10003, DSP_DONE = 0xDCD10003,
DSP_SYNC = 0xDCD10004, DSP_SYNC = 0xDCD10004,
DSP_FRAME_END = 0xDCD10005, DSP_FRAME_END = 0xDCD10005,
}; };
// UCode is forwarding mails to PrepareBootUCode // UCode is forwarding mails to PrepareBootUCode

36
Source/Core/Core/HW/DVDInterface.cpp
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@ -30,35 +30,35 @@ namespace DVDInterface
// internal hardware addresses // internal hardware addresses
enum enum
{ {
DI_STATUS_REGISTER = 0x00, DI_STATUS_REGISTER = 0x00,
DI_COVER_REGISTER = 0x04, DI_COVER_REGISTER = 0x04,
DI_COMMAND_0 = 0x08, DI_COMMAND_0 = 0x08,
DI_COMMAND_1 = 0x0C, DI_COMMAND_1 = 0x0C,
DI_COMMAND_2 = 0x10, DI_COMMAND_2 = 0x10,
DI_DMA_ADDRESS_REGISTER = 0x14, DI_DMA_ADDRESS_REGISTER = 0x14,
DI_DMA_LENGTH_REGISTER = 0x18, DI_DMA_LENGTH_REGISTER = 0x18,
DI_DMA_CONTROL_REGISTER = 0x1C, DI_DMA_CONTROL_REGISTER = 0x1C,
DI_IMMEDIATE_DATA_BUFFER = 0x20, DI_IMMEDIATE_DATA_BUFFER = 0x20,
DI_CONFIG_REGISTER = 0x24 DI_CONFIG_REGISTER = 0x24
}; };
// DVD IntteruptTypes // DVD IntteruptTypes
enum DI_InterruptType enum DI_InterruptType
{ {
INT_DEINT = 0, INT_DEINT = 0,
INT_TCINT = 1, INT_TCINT = 1,
INT_BRKINT = 2, INT_BRKINT = 2,
INT_CVRINT = 3, INT_CVRINT = 3,
}; };
// debug commands which may be ORd // debug commands which may be ORd
enum enum
{ {
STOP_DRIVE = 0, STOP_DRIVE = 0,
START_DRIVE = 0x100, START_DRIVE = 0x100,
ACCEPT_COPY = 0x4000, ACCEPT_COPY = 0x4000,
DISC_CHECK = 0x8000, DISC_CHECK = 0x8000,
}; };
// DI Status Register // DI Status Register

104
Source/Core/Core/HW/DVDInterface.h
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@ -43,65 +43,65 @@ void Write32(const u32 _iValue, const u32 _iAddress);
// Not sure about endianness here. I'll just name them like this... // Not sure about endianness here. I'll just name them like this...
enum DIErrorLow enum DIErrorLow
{ {
ERROR_READY = 0x00000000, // Ready. ERROR_READY = 0x00000000, // Ready.
ERROR_COVER_L = 0x01000000, // Cover is opened. ERROR_COVER_L = 0x01000000, // Cover is opened.
ERROR_CHANGE_DISK = 0x02000000, // Disk change. ERROR_CHANGE_DISK = 0x02000000, // Disk change.
ERROR_NO_DISK = 0x03000000, // No Disk. ERROR_NO_DISK = 0x03000000, // No Disk.
ERROR_MOTOR_STOP_L = 0x04000000, // Motor stop. ERROR_MOTOR_STOP_L = 0x04000000, // Motor stop.
ERROR_NO_DISKID_L = 0x05000000 // Disk ID not read. ERROR_NO_DISKID_L = 0x05000000 // Disk ID not read.
}; };
enum DIErrorHigh enum DIErrorHigh
{ {
ERROR_NONE = 0x000000, // No error. ERROR_NONE = 0x000000, // No error.
ERROR_MOTOR_STOP_H = 0x020400, // Motor stopped. ERROR_MOTOR_STOP_H = 0x020400, // Motor stopped.
ERROR_NO_DISKID_H = 0x020401, // Disk ID not read. ERROR_NO_DISKID_H = 0x020401, // Disk ID not read.
ERROR_COVER_H = 0x023a00, // Medium not present / Cover opened. ERROR_COVER_H = 0x023a00, // Medium not present / Cover opened.
ERROR_SEEK_NDONE = 0x030200, // No Seek complete. ERROR_SEEK_NDONE = 0x030200, // No Seek complete.
ERROR_READ = 0x031100, // UnRecoverd read error. ERROR_READ = 0x031100, // UnRecoverd read error.
ERROR_PROTOCOL = 0x040800, // Transfer protocol error. ERROR_PROTOCOL = 0x040800, // Transfer protocol error.
ERROR_INV_CMD = 0x052000, // Invalid command operation code. ERROR_INV_CMD = 0x052000, // Invalid command operation code.
ERROR_AUDIO_BUF = 0x052001, // Audio Buffer not set. ERROR_AUDIO_BUF = 0x052001, // Audio Buffer not set.
ERROR_BLOCK_OOB = 0x052100, // Logical block address out of bounds. ERROR_BLOCK_OOB = 0x052100, // Logical block address out of bounds.
ERROR_INV_FIELD = 0x052400, // Invalid Field in command packet. ERROR_INV_FIELD = 0x052400, // Invalid Field in command packet.
ERROR_INV_AUDIO = 0x052401, // Invalid audio command. ERROR_INV_AUDIO = 0x052401, // Invalid audio command.
ERROR_INV_PERIOD = 0x052402, // Configuration out of permitted period. ERROR_INV_PERIOD = 0x052402, // Configuration out of permitted period.
ERROR_END_USR_AREA = 0x056300, // End of user area encountered on this track. ERROR_END_USR_AREA = 0x056300, // End of user area encountered on this track.
ERROR_MEDIUM = 0x062800, // Medium may have changed. ERROR_MEDIUM = 0x062800, // Medium may have changed.
ERROR_MEDIUM_REQ = 0x0b5a01 // Operator medium removal request. ERROR_MEDIUM_REQ = 0x0b5a01 // Operator medium removal request.
}; };
enum DICommand enum DICommand
{ {
DVDLowInquiry = 0x12, DVDLowInquiry = 0x12,
DVDLowReadDiskID = 0x70, DVDLowReadDiskID = 0x70,
DVDLowRead = 0x71, DVDLowRead = 0x71,
DVDLowWaitForCoverClose = 0x79, DVDLowWaitForCoverClose = 0x79,
DVDLowGetCoverReg = 0x7a, // DVDLowPrepareCoverRegister? DVDLowGetCoverReg = 0x7a, // DVDLowPrepareCoverRegister?
DVDLowNotifyReset = 0x7e, DVDLowNotifyReset = 0x7e,
DVDLowReadDvdPhysical = 0x80, DVDLowReadDvdPhysical = 0x80,
DVDLowReadDvdCopyright = 0x81, DVDLowReadDvdCopyright = 0x81,
DVDLowReadDvdDiscKey = 0x82, DVDLowReadDvdDiscKey = 0x82,
DVDLowClearCoverInterrupt = 0x86, DVDLowClearCoverInterrupt = 0x86,
DVDLowGetCoverStatus = 0x88, DVDLowGetCoverStatus = 0x88,
DVDLowReset = 0x8a, DVDLowReset = 0x8a,
DVDLowOpenPartition = 0x8b, DVDLowOpenPartition = 0x8b,
DVDLowClosePartition = 0x8c, DVDLowClosePartition = 0x8c,
DVDLowUnencryptedRead = 0x8d, DVDLowUnencryptedRead = 0x8d,
DVDLowEnableDvdVideo = 0x8e, DVDLowEnableDvdVideo = 0x8e,
DVDLowReportKey = 0xa4, DVDLowReportKey = 0xa4,
DVDLowSeek = 0xab, DVDLowSeek = 0xab,
DVDLowReadDvd = 0xd0, DVDLowReadDvd = 0xd0,
DVDLowReadDvdConfig = 0xd1, DVDLowReadDvdConfig = 0xd1,
DVDLowStopLaser = 0xd2, DVDLowStopLaser = 0xd2,
DVDLowOffset = 0xd9, DVDLowOffset = 0xd9,
DVDLowReadDiskBca = 0xda, DVDLowReadDiskBca = 0xda,
DVDLowRequestDiscStatus = 0xdb, DVDLowRequestDiscStatus = 0xdb,
DVDLowRequestRetryNumber = 0xdc, DVDLowRequestRetryNumber = 0xdc,
DVDLowSetMaximumRotation = 0xdd, DVDLowSetMaximumRotation = 0xdd,
DVDLowSerMeasControl = 0xdf, DVDLowSerMeasControl = 0xdf,
DVDLowRequestError = 0xe0, DVDLowRequestError = 0xe0,
DVDLowStopMotor = 0xe3, DVDLowStopMotor = 0xe3,
DVDLowAudioBufferConfig = 0xe4 DVDLowAudioBufferConfig = 0xe4
}; };
} // end of namespace DVDInterface } // end of namespace DVDInterface

10
Source/Core/Core/HW/EXI_Channel.h
View File

@ -16,11 +16,11 @@ private:
enum enum
{ {
EXI_STATUS = 0, EXI_STATUS = 0,
EXI_DMAADDR = 1, EXI_DMAADDR = 1,
EXI_DMALENGTH = 2, EXI_DMALENGTH = 2,
EXI_DMACONTROL = 3, EXI_DMACONTROL = 3,
EXI_IMMDATA = 4 EXI_IMMDATA = 4
}; };
const char* Debug_GetRegisterName(u32 _register) const char* Debug_GetRegisterName(u32 _register)
{ {

6
Source/Core/Core/HW/EXI_DeviceAD16.h
View File

@ -16,9 +16,9 @@ public:
private: private:
enum enum
{ {
init = 0x00, init = 0x00,
write = 0xa0, write = 0xa0,
read = 0xa2 read = 0xa2
}; };
union UAD16Reg union UAD16Reg

212
Source/Core/Core/HW/EXI_DeviceEthernet.h
View File

@ -14,172 +14,172 @@
// Network Control Register A // Network Control Register A
enum NCRA enum NCRA
{ {
NCRA_RESET = 0x01, // RESET NCRA_RESET = 0x01, // RESET
NCRA_ST0 = 0x02, // Start transmit command/status NCRA_ST0 = 0x02, // Start transmit command/status
NCRA_ST1 = 0x04, // " NCRA_ST1 = 0x04, // "
NCRA_SR = 0x08 // Start Receive NCRA_SR = 0x08 // Start Receive
}; };
// Network Control Register B // Network Control Register B
enum NCRB enum NCRB
{ {
NCRB_PR = 0x01, // Promiscuous Mode NCRB_PR = 0x01, // Promiscuous Mode
NCRB_CA = 0x02, // Capture Effect Mode NCRB_CA = 0x02, // Capture Effect Mode
NCRB_PM = 0x04, // Pass Multicast NCRB_PM = 0x04, // Pass Multicast
NCRB_PB = 0x08, // Pass Bad Frame NCRB_PB = 0x08, // Pass Bad Frame
NCRB_AB = 0x10, // Accept Broadcast NCRB_AB = 0x10, // Accept Broadcast
NCRB_HBD = 0x20, // reserved NCRB_HBD = 0x20, // reserved
NCRB_RXINTC = 0xC0 // Receive Interrupt Counter (mask) NCRB_RXINTC = 0xC0 // Receive Interrupt Counter (mask)
}; };
// Interrupt Mask Register // Interrupt Mask Register
// Interrupt Register // Interrupt Register
enum Interrupts enum Interrupts
{ {
INT_FRAG = 0x01, // Fragment Counter INT_FRAG = 0x01, // Fragment Counter
INT_R = 0x02, // Receive INT_R = 0x02, // Receive
INT_T = 0x04, // Transmit INT_T = 0x04, // Transmit
INT_R_ERR = 0x08, // Receive Error INT_R_ERR = 0x08, // Receive Error
INT_T_ERR = 0x10, // Transmit Error INT_T_ERR = 0x10, // Transmit Error
INT_FIFO_ERR = 0x20, // FIFO Error INT_FIFO_ERR = 0x20, // FIFO Error
INT_BUS_ERR = 0x40, // BUS Error INT_BUS_ERR = 0x40, // BUS Error
INT_RBF = 0x80 // RX Buffer Full INT_RBF = 0x80 // RX Buffer Full
}; };
// NWAY Configuration Register // NWAY Configuration Register
enum NWAYC enum NWAYC
{ {
NWAYC_FD = 0x01, // Full Duplex Mode NWAYC_FD = 0x01, // Full Duplex Mode
NWAYC_PS100_10 = 0x02, // Port Select 100/10 NWAYC_PS100_10 = 0x02, // Port Select 100/10
NWAYC_ANE = 0x04, // Autonegotiate enable NWAYC_ANE = 0x04, // Autonegotiate enable
// Autonegotiation status bits... // Autonegotiation status bits...
NWAYC_NTTEST = 0x40, // Reserved NWAYC_NTTEST = 0x40, // Reserved
NWAYC_LTE = 0x80 // Link Test Enable NWAYC_LTE = 0x80 // Link Test Enable
}; };
enum NWAYS enum NWAYS
{ {
NWAYS_LS10 = 0x01, NWAYS_LS10 = 0x01,
NWAYS_LS100 = 0x02, NWAYS_LS100 = 0x02,
NWAYS_LPNWAY = 0x04, NWAYS_LPNWAY = 0x04,
NWAYS_ANCLPT = 0x08, NWAYS_ANCLPT = 0x08,
NWAYS_100TXF = 0x10, NWAYS_100TXF = 0x10,
NWAYS_100TXH = 0x20, NWAYS_100TXH = 0x20,
NWAYS_10TXF = 0x40, NWAYS_10TXF = 0x40,
NWAYS_10TXH = 0x80 NWAYS_10TXH = 0x80
}; };
enum MISC1 enum MISC1
{ {
MISC1_BURSTDMA = 0x01, MISC1_BURSTDMA = 0x01,
MISC1_DISLDMA = 0x02, MISC1_DISLDMA = 0x02,
MISC1_TPF = 0x04, MISC1_TPF = 0x04,
MISC1_TPH = 0x08, MISC1_TPH = 0x08,
MISC1_TXF = 0x10, MISC1_TXF = 0x10,
MISC1_TXH = 0x20, MISC1_TXH = 0x20,
MISC1_TXFIFORST = 0x40, MISC1_TXFIFORST = 0x40,
MISC1_RXFIFORST = 0x80 MISC1_RXFIFORST = 0x80
}; };
enum MISC2 enum MISC2
{ {
MISC2_HBRLEN0 = 0x01, MISC2_HBRLEN0 = 0x01,
MISC2_HBRLEN1 = 0x02, MISC2_HBRLEN1 = 0x02,
MISC2_RUNTSIZE = 0x04, MISC2_RUNTSIZE = 0x04,
MISC2_DREQBCTRL = 0x08, MISC2_DREQBCTRL = 0x08,
MISC2_RINTSEL = 0x10, MISC2_RINTSEL = 0x10,
MISC2_ITPSEL = 0x20, MISC2_ITPSEL = 0x20,
MISC2_A11A8EN = 0x40, MISC2_A11A8EN = 0x40,
MISC2_AUTORCVR = 0x80 MISC2_AUTORCVR = 0x80
}; };
enum enum
{ {
BBA_NCRA = 0x00, BBA_NCRA = 0x00,
BBA_NCRB = 0x01, BBA_NCRB = 0x01,
BBA_LTPS = 0x04, BBA_LTPS = 0x04,
BBA_LRPS = 0x05, BBA_LRPS = 0x05,
BBA_IMR = 0x08, BBA_IMR = 0x08,
BBA_IR = 0x09, BBA_IR = 0x09,
BBA_BP = 0x0a, BBA_BP = 0x0a,
BBA_TLBP = 0x0c, BBA_TLBP = 0x0c,
BBA_TWP = 0x0e, BBA_TWP = 0x0e,
BBA_IOB = 0x10, BBA_IOB = 0x10,
BBA_TRP = 0x12, BBA_TRP = 0x12,
BBA_RWP = 0x16, BBA_RWP = 0x16,
BBA_RRP = 0x18, BBA_RRP = 0x18,
BBA_RHBP = 0x1a, BBA_RHBP = 0x1a,
BBA_RXINTT = 0x14, BBA_RXINTT = 0x14,
BBA_NAFR_PAR0 = 0x20, BBA_NAFR_PAR0 = 0x20,
BBA_NAFR_PAR1 = 0x21, BBA_NAFR_PAR1 = 0x21,
BBA_NAFR_PAR2 = 0x22, BBA_NAFR_PAR2 = 0x22,
BBA_NAFR_PAR3 = 0x23, BBA_NAFR_PAR3 = 0x23,
BBA_NAFR_PAR4 = 0x24, BBA_NAFR_PAR4 = 0x24,
BBA_NAFR_PAR5 = 0x25, BBA_NAFR_PAR5 = 0x25,
BBA_NAFR_MAR0 = 0x26, BBA_NAFR_MAR0 = 0x26,
BBA_NAFR_MAR1 = 0x27, BBA_NAFR_MAR1 = 0x27,
BBA_NAFR_MAR2 = 0x28, BBA_NAFR_MAR2 = 0x28,
BBA_NAFR_MAR3 = 0x29, BBA_NAFR_MAR3 = 0x29,
BBA_NAFR_MAR4 = 0x2a, BBA_NAFR_MAR4 = 0x2a,
BBA_NAFR_MAR5 = 0x2b, BBA_NAFR_MAR5 = 0x2b,
BBA_NAFR_MAR6 = 0x2c, BBA_NAFR_MAR6 = 0x2c,
BBA_NAFR_MAR7 = 0x2d, BBA_NAFR_MAR7 = 0x2d,
BBA_NWAYC = 0x30, BBA_NWAYC = 0x30,
BBA_NWAYS = 0x31, BBA_NWAYS = 0x31,
BBA_GCA = 0x32, BBA_GCA = 0x32,
BBA_MISC = 0x3d, BBA_MISC = 0x3d,
BBA_TXFIFOCNT = 0x3e, BBA_TXFIFOCNT = 0x3e,
BBA_WRTXFIFOD = 0x48, BBA_WRTXFIFOD = 0x48,
BBA_MISC2 = 0x50, BBA_MISC2 = 0x50,
BBA_SI_ACTRL = 0x5c, BBA_SI_ACTRL = 0x5c,
BBA_SI_STATUS = 0x5d, BBA_SI_STATUS = 0x5d,
BBA_SI_ACTRL2 = 0x60 BBA_SI_ACTRL2 = 0x60
}; };
enum enum
{ {
BBA_NUM_PAGES = 0x10, BBA_NUM_PAGES = 0x10,
BBA_PAGE_SIZE = 0x100, BBA_PAGE_SIZE = 0x100,
BBA_MEM_SIZE = BBA_NUM_PAGES * BBA_PAGE_SIZE BBA_MEM_SIZE = BBA_NUM_PAGES * BBA_PAGE_SIZE
}; };
enum { EXI_DEVTYPE_ETHER = 0x04020200 }; enum { EXI_DEVTYPE_ETHER = 0x04020200 };
enum SendStatus enum SendStatus
{ {
DESC_CC0 = 0x01, DESC_CC0 = 0x01,
DESC_CC1 = 0x02, DESC_CC1 = 0x02,
DESC_CC2 = 0x04, DESC_CC2 = 0x04,
DESC_CC3 = 0x08, DESC_CC3 = 0x08,
DESC_CRSLOST= 0x10, DESC_CRSLOST = 0x10,
DESC_UF = 0x20, DESC_UF = 0x20,
DESC_OWC = 0x40, DESC_OWC = 0x40,
DESC_OWN = 0x80 DESC_OWN = 0x80
}; };
enum RecvStatus enum RecvStatus
{ {
DESC_BF = 0x01, DESC_BF = 0x01,
DESC_CRC = 0x02, DESC_CRC = 0x02,
DESC_FAE = 0x04, DESC_FAE = 0x04,
DESC_FO = 0x08, DESC_FO = 0x08,
DESC_RW = 0x10, DESC_RW = 0x10,
DESC_MF = 0x20, DESC_MF = 0x20,
DESC_RF = 0x40, DESC_RF = 0x40,
DESC_RERR = 0x80 DESC_RERR = 0x80
}; };
#define BBA_RECV_SIZE 0x800 #define BBA_RECV_SIZE 0x800

30
Source/Core/Core/HW/EXI_DeviceMemoryCard.h
View File

@ -48,21 +48,21 @@ private:
enum enum
{ {
cmdNintendoID = 0x00, cmdNintendoID = 0x00,
cmdReadArray = 0x52, cmdReadArray = 0x52,
cmdArrayToBuffer = 0x53, cmdArrayToBuffer = 0x53,
cmdSetInterrupt = 0x81, cmdSetInterrupt = 0x81,
cmdWriteBuffer = 0x82, cmdWriteBuffer = 0x82,
cmdReadStatus = 0x83, cmdReadStatus = 0x83,
cmdReadID = 0x85, cmdReadID = 0x85,
cmdReadErrorBuffer = 0x86, cmdReadErrorBuffer = 0x86,
cmdWakeUp = 0x87, cmdWakeUp = 0x87,
cmdSleep = 0x88, cmdSleep = 0x88,
cmdClearStatus = 0x89, cmdClearStatus = 0x89,
cmdSectorErase = 0xF1, cmdSectorErase = 0xF1,
cmdPageProgram = 0xF2, cmdPageProgram = 0xF2,
cmdExtraByteProgram = 0xF3, cmdExtraByteProgram = 0xF3,
cmdChipErase = 0xF4, cmdChipErase = 0xF4,
}; };
std::string m_strFilename; std::string m_strFilename;

10
Source/Core/Core/HW/EXI_DeviceMic.h
View File

@ -26,11 +26,11 @@ private:
enum enum
{ {
cmdID = 0x00, cmdID = 0x00,
cmdGetStatus = 0x40, cmdGetStatus = 0x40,
cmdSetStatus = 0x80, cmdSetStatus = 0x80,
cmdGetBuffer = 0x20, cmdGetBuffer = 0x20,
cmdReset = 0xFF, cmdReset = 0xFF,
}; };
int slot; int slot;

28
Source/Core/Core/HW/Memmap.h
View File

@ -63,21 +63,21 @@ enum
// what will be reported in lowmem, and thus used by emulated software. // what will be reported in lowmem, and thus used by emulated software.
// Note: Writing to lowmem is done by IPL. If using retail IPL, it will // Note: Writing to lowmem is done by IPL. If using retail IPL, it will
// always be set to 24MB. // always be set to 24MB.
REALRAM_SIZE = 0x1800000, REALRAM_SIZE = 0x1800000,
RAM_SIZE = ROUND_UP_POW2(REALRAM_SIZE), RAM_SIZE = ROUND_UP_POW2(REALRAM_SIZE),
RAM_MASK = RAM_SIZE - 1, RAM_MASK = RAM_SIZE - 1,
FAKEVMEM_SIZE = 0x2000000, FAKEVMEM_SIZE = 0x2000000,
FAKEVMEM_MASK = FAKEVMEM_SIZE - 1, FAKEVMEM_MASK = FAKEVMEM_SIZE - 1,
L1_CACHE_SIZE = 0x40000, L1_CACHE_SIZE = 0x40000,
L1_CACHE_MASK = L1_CACHE_SIZE - 1, L1_CACHE_MASK = L1_CACHE_SIZE - 1,
EFB_SIZE = 0x200000, EFB_SIZE = 0x200000,
EFB_MASK = EFB_SIZE - 1, EFB_MASK = EFB_SIZE - 1,
IO_SIZE = 0x10000, IO_SIZE = 0x10000,
EXRAM_SIZE = 0x4000000, EXRAM_SIZE = 0x4000000,
EXRAM_MASK = EXRAM_SIZE - 1, EXRAM_MASK = EXRAM_SIZE - 1,
ADDR_MASK_HW_ACCESS = 0x0c000000, ADDR_MASK_HW_ACCESS = 0x0c000000,
ADDR_MASK_MEM1 = 0x20000000, ADDR_MASK_MEM1 = 0x20000000,
#ifndef _M_X64 #ifndef _M_X64
MEMVIEW32_MASK = 0x3FFFFFFF, MEMVIEW32_MASK = 0x3FFFFFFF,

18
Source/Core/Core/HW/MemoryInterface.cpp
View File

@ -14,15 +14,15 @@ namespace MemoryInterface
// internal hardware addresses // internal hardware addresses
enum enum
{ {
MEM_CHANNEL0_HI = 0x000, MEM_CHANNEL0_HI = 0x000,
MEM_CHANNEL0_LO = 0x002, MEM_CHANNEL0_LO = 0x002,
MEM_CHANNEL1_HI = 0x004, MEM_CHANNEL1_HI = 0x004,
MEM_CHANNEL1_LO = 0x006, MEM_CHANNEL1_LO = 0x006,
MEM_CHANNEL2_HI = 0x008, MEM_CHANNEL2_HI = 0x008,
MEM_CHANNEL2_LO = 0x00A, MEM_CHANNEL2_LO = 0x00A,
MEM_CHANNEL3_HI = 0x00C, MEM_CHANNEL3_HI = 0x00C,
MEM_CHANNEL3_LO = 0x00E, MEM_CHANNEL3_LO = 0x00E,
MEM_CHANNEL_CTRL = 0x010 MEM_CHANNEL_CTRL = 0x010
}; };
struct MIMemStruct struct MIMemStruct

18
Source/Core/Core/HW/ProcessorInterface.cpp
View File

@ -21,15 +21,15 @@ namespace ProcessorInterface
// Internal hardware addresses // Internal hardware addresses
enum enum
{ {
PI_INTERRUPT_CAUSE = 0x00, PI_INTERRUPT_CAUSE = 0x00,
PI_INTERRUPT_MASK = 0x04, PI_INTERRUPT_MASK = 0x04,
PI_FIFO_BASE = 0x0C, PI_FIFO_BASE = 0x0C,
PI_FIFO_END = 0x10, PI_FIFO_END = 0x10,
PI_FIFO_WPTR = 0x14, PI_FIFO_WPTR = 0x14,
PI_FIFO_RESET = 0x18, // ??? - GXAbortFrame writes to it PI_FIFO_RESET = 0x18, // ??? - GXAbortFrame writes to it
PI_RESET_CODE = 0x24, PI_RESET_CODE = 0x24,
PI_FLIPPER_REV = 0x2C, PI_FLIPPER_REV = 0x2C,
PI_FLIPPER_UNK = 0x30 // BS1 writes 0x0245248A to it - prolly some bootstrap thing PI_FLIPPER_UNK = 0x30 // BS1 writes 0x0245248A to it - prolly some bootstrap thing
}; };

4
Source/Core/Core/HW/ProcessorInterface.h
View File

@ -15,12 +15,12 @@ namespace ProcessorInterface
enum InterruptCause enum InterruptCause
{ {
INT_CAUSE_PI = 0x1, // YAGCD says: GP runtime error INT_CAUSE_PI = 0x1, // YAGCD says: GP runtime error
INT_CAUSE_RSW = 0x2, // Reset Switch INT_CAUSE_RSW = 0x2, // Reset Switch
INT_CAUSE_DI = 0x4, // DVD interrupt INT_CAUSE_DI = 0x4, // DVD interrupt
INT_CAUSE_SI = 0x8, // Serial interface INT_CAUSE_SI = 0x8, // Serial interface
INT_CAUSE_EXI = 0x10, // Expansion interface INT_CAUSE_EXI = 0x10, // Expansion interface
INT_CAUSE_AI = 0x20, // Audio Interface Streaming INT_CAUSE_AI = 0x20, // Audio Interface Streaming
INT_CAUSE_DSP = 0x40, // DSP interface INT_CAUSE_DSP = 0x40, // DSP interface
INT_CAUSE_MEMORY = 0x80, // Memory interface INT_CAUSE_MEMORY = 0x80, // Memory interface
INT_CAUSE_VI = 0x100, // Video interface INT_CAUSE_VI = 0x100, // Video interface

36
Source/Core/Core/HW/SI.cpp
View File

@ -27,30 +27,30 @@ void UpdateInterrupts();
// SI Interrupt Types // SI Interrupt Types
enum SIInterruptType enum SIInterruptType
{ {
INT_RDSTINT = 0, INT_RDSTINT = 0,
INT_TCINT = 1, INT_TCINT = 1,
}; };
static void GenerateSIInterrupt(SIInterruptType _SIInterrupt); static void GenerateSIInterrupt(SIInterruptType _SIInterrupt);
// SI Internal Hardware Addresses // SI Internal Hardware Addresses
enum enum
{ {
SI_CHANNEL_0_OUT = 0x00, SI_CHANNEL_0_OUT = 0x00,
SI_CHANNEL_0_IN_HI = 0x04, SI_CHANNEL_0_IN_HI = 0x04,
SI_CHANNEL_0_IN_LO = 0x08, SI_CHANNEL_0_IN_LO = 0x08,
SI_CHANNEL_1_OUT = 0x0C, SI_CHANNEL_1_OUT = 0x0C,
SI_CHANNEL_1_IN_HI = 0x10, SI_CHANNEL_1_IN_HI = 0x10,
SI_CHANNEL_1_IN_LO = 0x14, SI_CHANNEL_1_IN_LO = 0x14,
SI_CHANNEL_2_OUT = 0x18, SI_CHANNEL_2_OUT = 0x18,
SI_CHANNEL_2_IN_HI = 0x1C, SI_CHANNEL_2_IN_HI = 0x1C,
SI_CHANNEL_2_IN_LO = 0x20, SI_CHANNEL_2_IN_LO = 0x20,
SI_CHANNEL_3_OUT = 0x24, SI_CHANNEL_3_OUT = 0x24,
SI_CHANNEL_3_IN_HI = 0x28, SI_CHANNEL_3_IN_HI = 0x28,
SI_CHANNEL_3_IN_LO = 0x2C, SI_CHANNEL_3_IN_LO = 0x2C,
SI_POLL = 0x30, SI_POLL = 0x30,
SI_COM_CSR = 0x34, SI_COM_CSR = 0x34,
SI_STATUS_REG = 0x38, SI_STATUS_REG = 0x38,
SI_EXI_CLOCK_COUNT = 0x3C, SI_EXI_CLOCK_COUNT = 0x3C,
}; };
// SI Channel Output // SI Channel Output

22
Source/Core/Core/HW/SI_Device.h
View File

@ -25,17 +25,17 @@ class PointerWrap;
// SI Device IDs for emulator use // SI Device IDs for emulator use
enum TSIDevices enum TSIDevices
{ {
SI_NONE = SI_ERROR_NO_RESPONSE, SI_NONE = SI_ERROR_NO_RESPONSE,
SI_N64_MIC = 0x00010000, SI_N64_MIC = 0x00010000,
SI_N64_KEYBOARD = 0x00020000, SI_N64_KEYBOARD = 0x00020000,
SI_N64_MOUSE = 0x02000000, SI_N64_MOUSE = 0x02000000,
SI_N64_CONTROLLER = 0x05000000, SI_N64_CONTROLLER = 0x05000000,
SI_GBA = 0x00040000, SI_GBA = 0x00040000,
SI_GC_CONTROLLER = (SI_TYPE_GC | SI_GC_STANDARD), SI_GC_CONTROLLER = (SI_TYPE_GC | SI_GC_STANDARD),
SI_GC_KEYBOARD = (SI_TYPE_GC | 0x00200000), SI_GC_KEYBOARD = (SI_TYPE_GC | 0x00200000),
SI_GC_STEERING = SI_TYPE_GC, // (shuffle2)I think the "chainsaw" is the same (Or else it's just standard) SI_GC_STEERING = SI_TYPE_GC, // (shuffle2)I think the "chainsaw" is the same (Or else it's just standard)
SI_DANCEMAT = (SI_TYPE_GC | SI_GC_STANDARD | 0x00000300), SI_DANCEMAT = (SI_TYPE_GC | SI_GC_STANDARD | 0x00000300),
SI_AM_BASEBOARD = 0x10110800 // gets ORd with dipswitch state SI_AM_BASEBOARD = 0x10110800 // gets ORd with dipswitch state
}; };
// For configuration use, since some devices can have the same SI Device ID // For configuration use, since some devices can have the same SI Device ID

4
Source/Core/Core/HW/SI_DeviceAMBaseboard.h
View File

@ -11,8 +11,8 @@ class CSIDevice_AMBaseboard : public ISIDevice
private: private:
enum EBufferCommands enum EBufferCommands
{ {
CMD_RESET = 0x00, CMD_RESET = 0x00,
CMD_GCAM = 0x70, CMD_GCAM = 0x70,
}; };
public: public:

10
Source/Core/Core/HW/SI_DeviceDanceMat.h
View File

@ -17,16 +17,16 @@ private:
// Commands // Commands
enum EBufferCommands enum EBufferCommands
{ {
CMD_RESET = 0x00, CMD_RESET = 0x00,
CMD_DIRECT = 0x40, CMD_DIRECT = 0x40,
CMD_ORIGIN = 0x41, CMD_ORIGIN = 0x41,
CMD_RECALIBRATE = 0x42, CMD_RECALIBRATE = 0x42,
}; };
struct SOrigin struct SOrigin
{ {
u8 uCommand;// Maybe should be button bits? u8 uCommand;// Maybe should be button bits?
u8 unk_1; // ..and this would be the other half u8 unk_1; // ..and this would be the other half
u8 uOriginStickX; u8 uOriginStickX;
u8 uOriginStickY; u8 uOriginStickY;
u8 uSubStickStickX; u8 uSubStickStickX;

8
Source/Core/Core/HW/SI_DeviceGBA.h
View File

@ -22,10 +22,10 @@ public:
private: private:
enum EJoybusCmds enum EJoybusCmds
{ {
CMD_RESET = 0xff, CMD_RESET = 0xff,
CMD_STATUS = 0x00, CMD_STATUS = 0x00,
CMD_READ = 0x14, CMD_READ = 0x14,
CMD_WRITE = 0x15 CMD_WRITE = 0x15
}; };
sf::SocketTCP client; sf::SocketTCP client;

8
Source/Core/Core/HW/SI_DeviceGCController.h
View File

@ -17,10 +17,10 @@ private:
// Commands // Commands
enum EBufferCommands enum EBufferCommands
{ {
CMD_RESET = 0x00, CMD_RESET = 0x00,
CMD_DIRECT = 0x40, CMD_DIRECT = 0x40,
CMD_ORIGIN = 0x41, CMD_ORIGIN = 0x41,
CMD_RECALIBRATE = 0x42, CMD_RECALIBRATE = 0x42,
}; };
struct SOrigin struct SOrigin

10
Source/Core/Core/HW/SI_DeviceGCSteeringWheel.h
View File

@ -17,16 +17,16 @@ private:
// Commands // Commands
enum EBufferCommands enum EBufferCommands
{ {
CMD_RESET = 0x00, CMD_RESET = 0x00,
CMD_ORIGIN = 0x41, CMD_ORIGIN = 0x41,
CMD_RECALIBRATE = 0x42, CMD_RECALIBRATE = 0x42,
CMD_MOTOR_OFF = 0xff, CMD_MOTOR_OFF = 0xff,
}; };
struct SOrigin struct SOrigin
{ {
u8 uCommand;// Maybe should be button bits? u8 uCommand;// Maybe should be button bits?
u8 unk_1; // ..and this would be the other half u8 unk_1; // ..and this would be the other half
u8 uOriginStickX; u8 uOriginStickX;
u8 uOriginStickY; u8 uOriginStickY;
u8 uSubStickStickX; u8 uSubStickStickX;

120
Source/Core/Core/HW/VideoInterface.h
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@ -35,66 +35,66 @@ namespace VideoInterface
// VI Internal Hardware Addresses // VI Internal Hardware Addresses
enum enum
{ {
VI_VERTICAL_TIMING = 0x00, VI_VERTICAL_TIMING = 0x00,
VI_CONTROL_REGISTER = 0x02, VI_CONTROL_REGISTER = 0x02,
VI_HORIZONTAL_TIMING_0_HI = 0x04, VI_HORIZONTAL_TIMING_0_HI = 0x04,
VI_HORIZONTAL_TIMING_0_LO = 0x06, VI_HORIZONTAL_TIMING_0_LO = 0x06,
VI_HORIZONTAL_TIMING_1_HI = 0x08, VI_HORIZONTAL_TIMING_1_HI = 0x08,
VI_HORIZONTAL_TIMING_1_LO = 0x0a, VI_HORIZONTAL_TIMING_1_LO = 0x0a,
VI_VBLANK_TIMING_ODD_HI = 0x0c, VI_VBLANK_TIMING_ODD_HI = 0x0c,
VI_VBLANK_TIMING_ODD_LO = 0x0e, VI_VBLANK_TIMING_ODD_LO = 0x0e,
VI_VBLANK_TIMING_EVEN_HI = 0x10, VI_VBLANK_TIMING_EVEN_HI = 0x10,
VI_VBLANK_TIMING_EVEN_LO = 0x12, VI_VBLANK_TIMING_EVEN_LO = 0x12,
VI_BURST_BLANKING_ODD_HI = 0x14, VI_BURST_BLANKING_ODD_HI = 0x14,
VI_BURST_BLANKING_ODD_LO = 0x16, VI_BURST_BLANKING_ODD_LO = 0x16,
VI_BURST_BLANKING_EVEN_HI = 0x18, VI_BURST_BLANKING_EVEN_HI = 0x18,
VI_BURST_BLANKING_EVEN_LO = 0x1a, VI_BURST_BLANKING_EVEN_LO = 0x1a,
VI_FB_LEFT_TOP_HI = 0x1c, // FB_LEFT_TOP is first half of XFB info VI_FB_LEFT_TOP_HI = 0x1c, // FB_LEFT_TOP is first half of XFB info
VI_FB_LEFT_TOP_LO = 0x1e, VI_FB_LEFT_TOP_LO = 0x1e,
VI_FB_RIGHT_TOP_HI = 0x20, // FB_RIGHT_TOP is only used in 3D mode VI_FB_RIGHT_TOP_HI = 0x20, // FB_RIGHT_TOP is only used in 3D mode
VI_FB_RIGHT_TOP_LO = 0x22, VI_FB_RIGHT_TOP_LO = 0x22,
VI_FB_LEFT_BOTTOM_HI = 0x24, // FB_LEFT_BOTTOM is second half of XFB info VI_FB_LEFT_BOTTOM_HI = 0x24, // FB_LEFT_BOTTOM is second half of XFB info
VI_FB_LEFT_BOTTOM_LO = 0x26, VI_FB_LEFT_BOTTOM_LO = 0x26,
VI_FB_RIGHT_BOTTOM_HI = 0x28, // FB_RIGHT_BOTTOM is only used in 3D mode VI_FB_RIGHT_BOTTOM_HI = 0x28, // FB_RIGHT_BOTTOM is only used in 3D mode
VI_FB_RIGHT_BOTTOM_LO = 0x2a, VI_FB_RIGHT_BOTTOM_LO = 0x2a,
VI_VERTICAL_BEAM_POSITION = 0x2c, VI_VERTICAL_BEAM_POSITION = 0x2c,
VI_HORIZONTAL_BEAM_POSITION = 0x2e, VI_HORIZONTAL_BEAM_POSITION = 0x2e,
VI_PRERETRACE_HI = 0x30, VI_PRERETRACE_HI = 0x30,
VI_PRERETRACE_LO = 0x32, VI_PRERETRACE_LO = 0x32,
VI_POSTRETRACE_HI = 0x34, VI_POSTRETRACE_HI = 0x34,
VI_POSTRETRACE_LO = 0x36, VI_POSTRETRACE_LO = 0x36,
VI_DISPLAY_INTERRUPT_2_HI = 0x38, VI_DISPLAY_INTERRUPT_2_HI = 0x38,
VI_DISPLAY_INTERRUPT_2_LO = 0x3a, VI_DISPLAY_INTERRUPT_2_LO = 0x3a,
VI_DISPLAY_INTERRUPT_3_HI = 0x3c, VI_DISPLAY_INTERRUPT_3_HI = 0x3c,
VI_DISPLAY_INTERRUPT_3_LO = 0x3e, VI_DISPLAY_INTERRUPT_3_LO = 0x3e,
VI_DISPLAY_LATCH_0_HI = 0x40, VI_DISPLAY_LATCH_0_HI = 0x40,
VI_DISPLAY_LATCH_0_LO = 0x42, VI_DISPLAY_LATCH_0_LO = 0x42,
VI_DISPLAY_LATCH_1_HI = 0x44, VI_DISPLAY_LATCH_1_HI = 0x44,
VI_DISPLAY_LATCH_1_LO = 0x46, VI_DISPLAY_LATCH_1_LO = 0x46,
VI_HSCALEW = 0x48, VI_HSCALEW = 0x48,
VI_HSCALER = 0x4a, VI_HSCALER = 0x4a,
VI_FILTER_COEF_0_HI = 0x4c, VI_FILTER_COEF_0_HI = 0x4c,
VI_FILTER_COEF_0_LO = 0x4e, VI_FILTER_COEF_0_LO = 0x4e,
VI_FILTER_COEF_1_HI = 0x50, VI_FILTER_COEF_1_HI = 0x50,
VI_FILTER_COEF_1_LO = 0x52, VI_FILTER_COEF_1_LO = 0x52,
VI_FILTER_COEF_2_HI = 0x54, VI_FILTER_COEF_2_HI = 0x54,
VI_FILTER_COEF_2_LO = 0x56, VI_FILTER_COEF_2_LO = 0x56,
VI_FILTER_COEF_3_HI = 0x58, VI_FILTER_COEF_3_HI = 0x58,
VI_FILTER_COEF_3_LO = 0x5a, VI_FILTER_COEF_3_LO = 0x5a,
VI_FILTER_COEF_4_HI = 0x5c, VI_FILTER_COEF_4_HI = 0x5c,
VI_FILTER_COEF_4_LO = 0x5e, VI_FILTER_COEF_4_LO = 0x5e,
VI_FILTER_COEF_5_HI = 0x60, VI_FILTER_COEF_5_HI = 0x60,
VI_FILTER_COEF_5_LO = 0x62, VI_FILTER_COEF_5_LO = 0x62,
VI_FILTER_COEF_6_HI = 0x64, VI_FILTER_COEF_6_HI = 0x64,
VI_FILTER_COEF_6_LO = 0x66, VI_FILTER_COEF_6_LO = 0x66,
VI_UNK_AA_REG_HI = 0x68, VI_UNK_AA_REG_HI = 0x68,
VI_UNK_AA_REG_LO = 0x6a, VI_UNK_AA_REG_LO = 0x6a,
VI_CLOCK = 0x6c, VI_CLOCK = 0x6c,
VI_DTV_STATUS = 0x6e, VI_DTV_STATUS = 0x6e,
VI_FBWIDTH = 0x70, VI_FBWIDTH = 0x70,
VI_BORDER_BLANK_END = 0x72, // Only used in debug video mode VI_BORDER_BLANK_END = 0x72, // Only used in debug video mode
VI_BORDER_BLANK_START = 0x74, // Only used in debug video mode VI_BORDER_BLANK_START = 0x74, // Only used in debug video mode
//VI_INTERLACE = 0x850, // ??? MYSTERY OLD CODE //VI_INTERLACE = 0x850, // ??? MYSTERY OLD CODE
}; };
union UVIVerticalTimingRegister union UVIVerticalTimingRegister

18
Source/Core/Core/HW/WII_IPC.cpp
View File

@ -32,17 +32,17 @@ namespace WII_IPCInterface
enum enum
{ {
IPC_PPCMSG = 0x00, IPC_PPCMSG = 0x00,
IPC_PPCCTRL = 0x04, IPC_PPCCTRL = 0x04,
IPC_ARMMSG = 0x08, IPC_ARMMSG = 0x08,
IPC_ARMCTRL = 0x0c, IPC_ARMCTRL = 0x0c,
PPC_IRQFLAG = 0x30, PPC_IRQFLAG = 0x30,
PPC_IRQMASK = 0x34, PPC_IRQMASK = 0x34,
ARM_IRQFLAG = 0x38, ARM_IRQFLAG = 0x38,
ARM_IRQMASK = 0x3c, ARM_IRQMASK = 0x3c,
GPIOB_OUT = 0xc0 // sensor bar power flag?? GPIOB_OUT = 0xc0 // sensor bar power flag??
}; };
struct CtrlRegister struct CtrlRegister

28
Source/Core/Core/HW/WII_IPC.h
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@ -13,23 +13,23 @@ namespace WII_IPCInterface
enum StarletInterruptCause enum StarletInterruptCause
{ {
INT_CAUSE_TIMER = 0x1, INT_CAUSE_TIMER = 0x1,
INT_CAUSE_NAND = 0x2, INT_CAUSE_NAND = 0x2,
INT_CAUSE_AES = 0x4, INT_CAUSE_AES = 0x4,
INT_CAUSE_SHA1 = 0x8, INT_CAUSE_SHA1 = 0x8,
INT_CAUSE_EHCI = 0x10, INT_CAUSE_EHCI = 0x10,
INT_CAUSE_OHCI0 = 0x20, INT_CAUSE_OHCI0 = 0x20,
INT_CAUSE_OHCI1 = 0x40, INT_CAUSE_OHCI1 = 0x40,
INT_CAUSE_SD = 0x80, INT_CAUSE_SD = 0x80,
INT_CAUSE_WIFI = 0x100, INT_CAUSE_WIFI = 0x100,
INT_CAUSE_GPIO_BROADWAY = 0x400, INT_CAUSE_GPIO_BROADWAY = 0x400,
INT_CAUSE_GPIO_STARLET = 0x800, INT_CAUSE_GPIO_STARLET = 0x800,
INT_CAUSE_RST_BUTTON = 0x40000, INT_CAUSE_RST_BUTTON = 0x40000,
INT_CAUSE_IPC_BROADWAY = 0x40000000, INT_CAUSE_IPC_BROADWAY = 0x40000000,
INT_CAUSE_IPC_STARLET = 0x80000000 INT_CAUSE_IPC_STARLET = 0x80000000
}; };
void Init(); void Init();

42
Source/Core/Core/IPC_HLE/WII_IPC_HLE_Device_FileIO.h
View File

@ -31,35 +31,35 @@ public:
private: private:
enum enum
{ {
ISFS_OPEN_READ = 1, ISFS_OPEN_READ = 1,
ISFS_OPEN_WRITE, ISFS_OPEN_WRITE = 2,
ISFS_OPEN_RW = (ISFS_OPEN_READ | ISFS_OPEN_WRITE) ISFS_OPEN_RW = (ISFS_OPEN_READ | ISFS_OPEN_WRITE)
}; };
enum enum
{ {
ISFS_FUNCNULL = 0, ISFS_FUNCNULL = 0,
ISFS_FUNCGETSTAT, ISFS_FUNCGETSTAT = 1,
ISFS_FUNCREADDIR, ISFS_FUNCREADDIR = 2,
ISFS_FUNCGETATTR, ISFS_FUNCGETATTR = 3,
ISFS_FUNCGETUSAGE ISFS_FUNCGETUSAGE = 4
}; };
enum enum
{ {
ISFS_IOCTL_FORMAT = 1, ISFS_IOCTL_FORMAT = 1,
ISFS_IOCTL_GETSTATS, ISFS_IOCTL_GETSTATS = 2,
ISFS_IOCTL_CREATEDIR, ISFS_IOCTL_CREATEDIR = 3,
ISFS_IOCTL_READDIR, ISFS_IOCTL_READDIR = 4,
ISFS_IOCTL_SETATTR, ISFS_IOCTL_SETATTR = 5,
ISFS_IOCTL_GETATTR, ISFS_IOCTL_GETATTR = 6,
ISFS_IOCTL_DELETE, ISFS_IOCTL_DELETE = 7,
ISFS_IOCTL_RENAME, ISFS_IOCTL_RENAME = 8,
ISFS_IOCTL_CREATEFILE, ISFS_IOCTL_CREATEFILE = 9,
ISFS_IOCTL_SETFILEVERCTRL, ISFS_IOCTL_SETFILEVERCTRL = 10,
ISFS_IOCTL_GETFILESTATS, ISFS_IOCTL_GETFILESTATS = 11,
ISFS_IOCTL_GETUSAGE, ISFS_IOCTL_GETUSAGE = 12,
ISFS_IOCTL_SHUTDOWN ISFS_IOCTL_SHUTDOWN = 13
}; };
u32 m_Mode; u32 m_Mode;

114
Source/Core/Core/IPC_HLE/WII_IPC_HLE_Device_es.h
View File

@ -37,64 +37,64 @@ public:
private: private:
enum enum
{ {
IOCTL_ES_ADDTICKET = 0x01, IOCTL_ES_ADDTICKET = 0x01,
IOCTL_ES_ADDTITLESTART = 0x02, IOCTL_ES_ADDTITLESTART = 0x02,
IOCTL_ES_ADDCONTENTSTART = 0x03, IOCTL_ES_ADDCONTENTSTART = 0x03,
IOCTL_ES_ADDCONTENTDATA = 0x04, IOCTL_ES_ADDCONTENTDATA = 0x04,
IOCTL_ES_ADDCONTENTFINISH = 0x05, IOCTL_ES_ADDCONTENTFINISH = 0x05,
IOCTL_ES_ADDTITLEFINISH = 0x06, IOCTL_ES_ADDTITLEFINISH = 0x06,
IOCTL_ES_GETDEVICEID = 0x07, IOCTL_ES_GETDEVICEID = 0x07,
IOCTL_ES_LAUNCH = 0x08, IOCTL_ES_LAUNCH = 0x08,
IOCTL_ES_OPENCONTENT = 0x09, IOCTL_ES_OPENCONTENT = 0x09,
IOCTL_ES_READCONTENT = 0x0A, IOCTL_ES_READCONTENT = 0x0A,
IOCTL_ES_CLOSECONTENT = 0x0B, IOCTL_ES_CLOSECONTENT = 0x0B,
IOCTL_ES_GETOWNEDTITLECNT = 0x0C, IOCTL_ES_GETOWNEDTITLECNT = 0x0C,
IOCTL_ES_GETOWNEDTITLES = 0x0D, IOCTL_ES_GETOWNEDTITLES = 0x0D,
IOCTL_ES_GETTITLECNT = 0x0E, IOCTL_ES_GETTITLECNT = 0x0E,
IOCTL_ES_GETTITLES = 0x0F, IOCTL_ES_GETTITLES = 0x0F,
IOCTL_ES_GETTITLECONTENTSCNT = 0x10, IOCTL_ES_GETTITLECONTENTSCNT = 0x10,
IOCTL_ES_GETTITLECONTENTS = 0x11, IOCTL_ES_GETTITLECONTENTS = 0x11,
IOCTL_ES_GETVIEWCNT = 0x12, IOCTL_ES_GETVIEWCNT = 0x12,
IOCTL_ES_GETVIEWS = 0x13, IOCTL_ES_GETVIEWS = 0x13,
IOCTL_ES_GETTMDVIEWCNT = 0x14, IOCTL_ES_GETTMDVIEWCNT = 0x14,
IOCTL_ES_GETTMDVIEWS = 0x15, IOCTL_ES_GETTMDVIEWS = 0x15,
IOCTL_ES_GETCONSUMPTION = 0x16, IOCTL_ES_GETCONSUMPTION = 0x16,
IOCTL_ES_DELETETITLE = 0x17, IOCTL_ES_DELETETITLE = 0x17,
IOCTL_ES_DELETETICKET = 0x18, IOCTL_ES_DELETETICKET = 0x18,
// IOCTL_ES_DIGETTMDVIEWSIZE = 0x19, // IOCTL_ES_DIGETTMDVIEWSIZE = 0x19,
// IOCTL_ES_DIGETTMDVIEW = 0x1A, // IOCTL_ES_DIGETTMDVIEW = 0x1A,
IOCTL_ES_DIGETTICKETVIEW = 0x1B, IOCTL_ES_DIGETTICKETVIEW = 0x1B,
IOCTL_ES_DIVERIFY = 0x1C, IOCTL_ES_DIVERIFY = 0x1C,
IOCTL_ES_GETTITLEDIR = 0x1D, IOCTL_ES_GETTITLEDIR = 0x1D,
IOCTL_ES_GETDEVICECERT = 0x1E, IOCTL_ES_GETDEVICECERT = 0x1E,
IOCTL_ES_IMPORTBOOT = 0x1F, IOCTL_ES_IMPORTBOOT = 0x1F,
IOCTL_ES_GETTITLEID = 0x20, IOCTL_ES_GETTITLEID = 0x20,
IOCTL_ES_SETUID = 0x21, IOCTL_ES_SETUID = 0x21,
IOCTL_ES_DELETETITLECONTENT = 0x22, IOCTL_ES_DELETETITLECONTENT = 0x22,
IOCTL_ES_SEEKCONTENT = 0x23, IOCTL_ES_SEEKCONTENT = 0x23,
IOCTL_ES_OPENTITLECONTENT = 0x24, IOCTL_ES_OPENTITLECONTENT = 0x24,
// IOCTL_ES_LAUNCHBC = 0x25, // IOCTL_ES_LAUNCHBC = 0x25,
// IOCTL_ES_EXPORTTITLEINIT = 0x26, // IOCTL_ES_EXPORTTITLEINIT = 0x26,
// IOCTL_ES_EXPORTCONTENTBEGIN = 0x27, // IOCTL_ES_EXPORTCONTENTBEGIN = 0x27,
// IOCTL_ES_EXPORTCONTENTDATA = 0x28, // IOCTL_ES_EXPORTCONTENTDATA = 0x28,
// IOCTL_ES_EXPORTCONTENTEND = 0x29, // IOCTL_ES_EXPORTCONTENTEND = 0x29,
// IOCTL_ES_EXPORTTITLEDONE = 0x2A, // IOCTL_ES_EXPORTTITLEDONE = 0x2A,
IOCTL_ES_ADDTMD = 0x2B, IOCTL_ES_ADDTMD = 0x2B,
IOCTL_ES_ENCRYPT = 0x2C, IOCTL_ES_ENCRYPT = 0x2C,
IOCTL_ES_DECRYPT = 0x2D, IOCTL_ES_DECRYPT = 0x2D,
IOCTL_ES_GETBOOT2VERSION = 0x2E, IOCTL_ES_GETBOOT2VERSION = 0x2E,
IOCTL_ES_ADDTITLECANCEL = 0x2F, IOCTL_ES_ADDTITLECANCEL = 0x2F,
IOCTL_ES_SIGN = 0x30, IOCTL_ES_SIGN = 0x30,
// IOCTL_ES_VERIFYSIGN = 0x31, // IOCTL_ES_VERIFYSIGN = 0x31,
IOCTL_ES_GETSTOREDCONTENTCNT = 0x32, IOCTL_ES_GETSTOREDCONTENTCNT = 0x32,
IOCTL_ES_GETSTOREDCONTENTS = 0x33, IOCTL_ES_GETSTOREDCONTENTS = 0x33,
IOCTL_ES_GETSTOREDTMDSIZE = 0x34, IOCTL_ES_GETSTOREDTMDSIZE = 0x34,
IOCTL_ES_GETSTOREDTMD = 0x35, IOCTL_ES_GETSTOREDTMD = 0x35,
IOCTL_ES_GETSHAREDCONTENTCNT = 0x36, IOCTL_ES_GETSHAREDCONTENTCNT = 0x36,
IOCTL_ES_GETSHAREDCONTENTS = 0x37, IOCTL_ES_GETSHAREDCONTENTS = 0x37,
IOCTL_ES_DELETESHAREDCONTENT = 0x38, IOCTL_ES_DELETESHAREDCONTENT = 0x38,
// //
IOCTL_ES_CHECKKOREAREGION = 0x45, IOCTL_ES_CHECKKOREAREGION = 0x45,
}; };
enum EErrorCodes enum EErrorCodes

20
Source/Core/Core/IPC_HLE/WII_IPC_HLE_Device_fs.h
View File

@ -50,16 +50,16 @@ private:
enum enum
{ {
IOCTL_GET_STATS = 0x02, IOCTL_GET_STATS = 0x02,
IOCTL_CREATE_DIR = 0x03, IOCTL_CREATE_DIR = 0x03,
IOCTLV_READ_DIR = 0x04, IOCTLV_READ_DIR = 0x04,
IOCTL_SET_ATTR = 0x05, IOCTL_SET_ATTR = 0x05,
IOCTL_GET_ATTR = 0x06, IOCTL_GET_ATTR = 0x06,
IOCTL_DELETE_FILE = 0x07, IOCTL_DELETE_FILE = 0x07,
IOCTL_RENAME_FILE = 0x08, IOCTL_RENAME_FILE = 0x08,
IOCTL_CREATE_FILE = 0x09, IOCTL_CREATE_FILE = 0x09,
IOCTLV_GETUSAGE = 0x0C, IOCTLV_GETUSAGE = 0x0C,
IOCTL_SHUTDOWN = 0x0D IOCTL_SHUTDOWN = 0x0D
}; };
s32 ExecuteCommand(u32 Parameter, u32 _BufferIn, u32 _BufferInSize, u32 _BufferOut, u32 _BufferOutSize); s32 ExecuteCommand(u32 Parameter, u32 _BufferIn, u32 _BufferInSize, u32 _BufferOut, u32 _BufferOutSize);

128
Source/Core/Core/IPC_HLE/WII_IPC_HLE_Device_net.h
View File

@ -33,40 +33,40 @@ struct netcfg_connection_t
{ {
enum enum
{ {
WIRED_IF = 1, // 0: wifi 1: wired WIRED_IF = 1, // 0: wifi 1: wired
DNS_DHCP = 2, // 0: manual 1: DHCP DNS_DHCP = 2, // 0: manual 1: DHCP
IP_DHCP = 4, // 0: manual 1: DHCP IP_DHCP = 4, // 0: manual 1: DHCP
USE_PROXY = 16, USE_PROXY = 16,
CONNECTION_TEST_OK = 32, CONNECTION_TEST_OK = 32,
CONNECTION_SELECTED = 128 CONNECTION_SELECTED = 128
}; };
enum enum
{ {
OPEN = 0, OPEN = 0,
WEP64 = 1, WEP64 = 1,
WEP128 = 2, WEP128 = 2,
WPA_TKIP = 4, WPA_TKIP = 4,
WPA2_AES = 5, WPA2_AES = 5,
WPA_AES = 6 WPA_AES = 6
}; };
enum status enum status
{ {
LINK_BUSY = 1, LINK_BUSY = 1,
LINK_NONE, LINK_NONE = 2,
LINK_WIRED, LINK_WIRED = 3,
LINK_WIFI_DOWN, LINK_WIFI_DOWN = 4,
LINK_WIFI_UP LINK_WIFI_UP = 5
}; };
enum enum
{ {
PERM_NONE = 0, PERM_NONE = 0,
PERM_SEND_MAIL = 1, PERM_SEND_MAIL = 1,
PERM_RECV_MAIL = 2, PERM_RECV_MAIL = 2,
PERM_DOWNLOAD = 4, PERM_DOWNLOAD = 4,
PERM_ALL = PERM_SEND_MAIL | PERM_RECV_MAIL | PERM_DOWNLOAD PERM_ALL = PERM_SEND_MAIL | PERM_RECV_MAIL | PERM_DOWNLOAD
}; };
// settings common to both wired and wireless connections // settings common to both wired and wireless connections
@ -119,28 +119,28 @@ struct network_config_t
enum nwc24_err_t enum nwc24_err_t
{ {
WC24_OK = 0, WC24_OK = 0,
WC24_ERR_FATAL = -1, WC24_ERR_FATAL = -1,
WC24_ERR_ID_NONEXISTANCE = -34, WC24_ERR_ID_NONEXISTANCE = -34,
WC24_ERR_ID_GENERATED = -35, WC24_ERR_ID_GENERATED = -35,
WC24_ERR_ID_REGISTERED = -36, WC24_ERR_ID_REGISTERED = -36,
WC24_ERR_ID_NOT_REGISTERED = -44, WC24_ERR_ID_NOT_REGISTERED = -44,
}; };
struct nwc24_config_t struct nwc24_config_t
{ {
enum enum
{ {
NWC24_IDCS_INITIAL = 0, NWC24_IDCS_INITIAL = 0,
NWC24_IDCS_GENERATED = 1, NWC24_IDCS_GENERATED = 1,
NWC24_IDCS_REGISTERED = 2 NWC24_IDCS_REGISTERED = 2
}; };
enum enum
{ {
URL_COUNT = 0x05, URL_COUNT = 0x05,
MAX_URL_LENGTH = 0x80, MAX_URL_LENGTH = 0x80,
MAX_EMAIL_LENGTH = 0x40, MAX_EMAIL_LENGTH = 0x40,
MAX_PASSWORD_LENGTH = 0x20, MAX_PASSWORD_LENGTH = 0x20,
}; };
@ -521,11 +521,11 @@ public:
private: private:
enum enum
{ {
IOCTL_NW24_GET_UNIVERSAL_TIME = 0x14, IOCTL_NW24_GET_UNIVERSAL_TIME = 0x14,
IOCTL_NW24_SET_UNIVERSAL_TIME = 0x15, IOCTL_NW24_SET_UNIVERSAL_TIME = 0x15,
IOCTL_NW24_UNIMPLEMENTED = 0x16, IOCTL_NW24_UNIMPLEMENTED = 0x16,
IOCTL_NW24_SET_RTC_COUNTER = 0x17, IOCTL_NW24_SET_RTC_COUNTER = 0x17,
IOCTL_NW24_GET_TIME_DIFF = 0x18, IOCTL_NW24_GET_TIME_DIFF = 0x18,
}; };
u64 rtc; u64 rtc;
@ -627,14 +627,14 @@ public:
private: private:
enum enum
{ {
IOCTLV_NCD_LOCKWIRELESSDRIVER = 0x1, // NCDLockWirelessDriver IOCTLV_NCD_LOCKWIRELESSDRIVER = 0x1, // NCDLockWirelessDriver
IOCTLV_NCD_UNLOCKWIRELESSDRIVER = 0x2, // NCDUnlockWirelessDriver IOCTLV_NCD_UNLOCKWIRELESSDRIVER = 0x2, // NCDUnlockWirelessDriver
IOCTLV_NCD_GETCONFIG = 0x3, // NCDiGetConfig IOCTLV_NCD_GETCONFIG = 0x3, // NCDiGetConfig
IOCTLV_NCD_SETCONFIG = 0x4, // NCDiSetConfig IOCTLV_NCD_SETCONFIG = 0x4, // NCDiSetConfig
IOCTLV_NCD_READCONFIG = 0x5, IOCTLV_NCD_READCONFIG = 0x5,
IOCTLV_NCD_WRITECONFIG = 0x6, IOCTLV_NCD_WRITECONFIG = 0x6,
IOCTLV_NCD_GETLINKSTATUS = 0x7, // NCDGetLinkStatus IOCTLV_NCD_GETLINKSTATUS = 0x7, // NCDGetLinkStatus
IOCTLV_NCD_GETWIRELESSMACADDRESS = 0x8, // NCDGetWirelessMacAddress IOCTLV_NCD_GETWIRELESSMACADDRESS = 0x8, // NCDGetWirelessMacAddress
}; };
WiiNetConfig config; WiiNetConfig config;
@ -655,24 +655,24 @@ public:
private: private:
enum enum
{ {
IOCTLV_WD_GET_MODE = 0x1001, // WD_GetMode IOCTLV_WD_GET_MODE = 0x1001, // WD_GetMode
IOCTLV_WD_SET_LINKSTATE = 0x1002, // WD_SetLinkState IOCTLV_WD_SET_LINKSTATE = 0x1002, // WD_SetLinkState
IOCTLV_WD_GET_LINKSTATE = 0x1003, // WD_GetLinkState IOCTLV_WD_GET_LINKSTATE = 0x1003, // WD_GetLinkState
IOCTLV_WD_SET_CONFIG = 0x1004, // WD_SetConfig IOCTLV_WD_SET_CONFIG = 0x1004, // WD_SetConfig
IOCTLV_WD_GET_CONFIG = 0x1005, // WD_GetConfig IOCTLV_WD_GET_CONFIG = 0x1005, // WD_GetConfig
IOCTLV_WD_CHANGE_BEACON = 0x1006, // WD_ChangeBeacon IOCTLV_WD_CHANGE_BEACON = 0x1006, // WD_ChangeBeacon
IOCTLV_WD_DISASSOC = 0x1007, // WD_DisAssoc IOCTLV_WD_DISASSOC = 0x1007, // WD_DisAssoc
IOCTLV_WD_MP_SEND_FRAME = 0x1008, // WD_MpSendFrame IOCTLV_WD_MP_SEND_FRAME = 0x1008, // WD_MpSendFrame
IOCTLV_WD_SEND_FRAME = 0x1009, // WD_SendFrame IOCTLV_WD_SEND_FRAME = 0x1009, // WD_SendFrame
IOCTLV_WD_SCAN = 0x100a, // WD_Scan IOCTLV_WD_SCAN = 0x100a, // WD_Scan
IOCTLV_WD_CALL_WL = 0x100c, // WD_CallWL IOCTLV_WD_CALL_WL = 0x100c, // WD_CallWL
IOCTLV_WD_MEASURE_CHANNEL = 0x100b, // WD_MeasureChannel IOCTLV_WD_MEASURE_CHANNEL = 0x100b, // WD_MeasureChannel
IOCTLV_WD_GET_LASTERROR = 0x100d, // WD_GetLastError IOCTLV_WD_GET_LASTERROR = 0x100d, // WD_GetLastError
IOCTLV_WD_GET_INFO = 0x100e, // WD_GetInfo IOCTLV_WD_GET_INFO = 0x100e, // WD_GetInfo
IOCTLV_WD_CHANGE_GAMEINFO = 0x100f, // WD_ChangeGameInfo IOCTLV_WD_CHANGE_GAMEINFO = 0x100f, // WD_ChangeGameInfo
IOCTLV_WD_CHANGE_VTSF = 0x1010, // WD_ChangeVTSF IOCTLV_WD_CHANGE_VTSF = 0x1010, // WD_ChangeVTSF
IOCTLV_WD_RECV_FRAME = 0x8000, // WD_ReceiveFrame IOCTLV_WD_RECV_FRAME = 0x8000, // WD_ReceiveFrame
IOCTLV_WD_RECV_NOTIFICATION = 0x8001 // WD_ReceiveNotification IOCTLV_WD_RECV_NOTIFICATION = 0x8001 // WD_ReceiveNotification
}; };
enum enum

60
Source/Core/Core/IPC_HLE/WII_IPC_HLE_Device_net_ssl.h
View File

@ -18,40 +18,40 @@
enum ssl_err_t enum ssl_err_t
{ {
SSL_OK = 0, SSL_OK = 0,
SSL_ERR_FAILED = -1, SSL_ERR_FAILED = -1,
SSL_ERR_RAGAIN = -2, SSL_ERR_RAGAIN = -2,
SSL_ERR_WAGAIN = -3, SSL_ERR_WAGAIN = -3,
SSL_ERR_SYSCALL = -5, SSL_ERR_SYSCALL = -5,
SSL_ERR_ZERO = -6, // read or write returned 0 SSL_ERR_ZERO = -6, // read or write returned 0
SSL_ERR_CAGAIN = -7, // BIO not connected SSL_ERR_CAGAIN = -7, // BIO not connected
SSL_ERR_ID = -8, // invalid SSL id SSL_ERR_ID = -8, // invalid SSL id
SSL_ERR_VCOMMONNAME = -9, // verify failed: common name SSL_ERR_VCOMMONNAME = -9, // verify failed: common name
SSL_ERR_VROOTCA = -10, // verify failed: root ca SSL_ERR_VROOTCA = -10, // verify failed: root ca
SSL_ERR_VCHAIN = -11, // verify failed: certificate chain SSL_ERR_VCHAIN = -11, // verify failed: certificate chain
SSL_ERR_VDATE = -12, // verify failed: date invalid SSL_ERR_VDATE = -12, // verify failed: date invalid
SSL_ERR_SERVER_CERT = -13, // certificate cert invalid SSL_ERR_SERVER_CERT = -13, // certificate cert invalid
}; };
enum SSL_IOCTL enum SSL_IOCTL
{ {
IOCTLV_NET_SSL_NEW = 0x01, IOCTLV_NET_SSL_NEW = 0x01,
IOCTLV_NET_SSL_CONNECT = 0x02, IOCTLV_NET_SSL_CONNECT = 0x02,
IOCTLV_NET_SSL_DOHANDSHAKE = 0x03, IOCTLV_NET_SSL_DOHANDSHAKE = 0x03,
IOCTLV_NET_SSL_READ = 0x04, IOCTLV_NET_SSL_READ = 0x04,
IOCTLV_NET_SSL_WRITE = 0x05, IOCTLV_NET_SSL_WRITE = 0x05,
IOCTLV_NET_SSL_SHUTDOWN = 0x06, IOCTLV_NET_SSL_SHUTDOWN = 0x06,
IOCTLV_NET_SSL_SETCLIENTCERT = 0x07, IOCTLV_NET_SSL_SETCLIENTCERT = 0x07,
IOCTLV_NET_SSL_SETCLIENTCERTDEFAULT = 0x08, IOCTLV_NET_SSL_SETCLIENTCERTDEFAULT = 0x08,
IOCTLV_NET_SSL_REMOVECLIENTCERT = 0x09, IOCTLV_NET_SSL_REMOVECLIENTCERT = 0x09,
IOCTLV_NET_SSL_SETROOTCA = 0x0A, IOCTLV_NET_SSL_SETROOTCA = 0x0A,
IOCTLV_NET_SSL_SETROOTCADEFAULT = 0x0B, IOCTLV_NET_SSL_SETROOTCADEFAULT = 0x0B,
IOCTLV_NET_SSL_DOHANDSHAKEEX = 0x0C, IOCTLV_NET_SSL_DOHANDSHAKEEX = 0x0C,
IOCTLV_NET_SSL_SETBUILTINROOTCA = 0x0D, IOCTLV_NET_SSL_SETBUILTINROOTCA = 0x0D,
IOCTLV_NET_SSL_SETBUILTINCLIENTCERT = 0x0E, IOCTLV_NET_SSL_SETBUILTINCLIENTCERT = 0x0E,
IOCTLV_NET_SSL_DISABLEVERIFYOPTIONFORDEBUG = 0x0F, IOCTLV_NET_SSL_DISABLEVERIFYOPTIONFORDEBUG = 0x0F,
IOCTLV_NET_SSL_DEBUGGETVERSION = 0x14, IOCTLV_NET_SSL_DEBUGGETVERSION = 0x14,
IOCTLV_NET_SSL_DEBUGGETTIME = 0x15, IOCTLV_NET_SSL_DEBUGGETTIME = 0x15,
}; };
typedef struct { typedef struct {

60
Source/Core/Core/IPC_HLE/WII_IPC_HLE_Device_sdio_slot0.h
View File

@ -29,26 +29,26 @@ private:
// SD Host Controller Registers // SD Host Controller Registers
enum enum
{ {
HCR_CLOCKCONTROL = 0x2C, HCR_CLOCKCONTROL = 0x2C,
HCR_SOFTWARERESET = 0x2F, HCR_SOFTWARERESET = 0x2F,
}; };
// IOCtl // IOCtl
enum enum
{ {
IOCTL_WRITEHCR = 0x01, IOCTL_WRITEHCR = 0x01,
IOCTL_READHCR = 0x02, IOCTL_READHCR = 0x02,
IOCTL_RESETCARD = 0x04, IOCTL_RESETCARD = 0x04,
IOCTL_SETCLK = 0x06, IOCTL_SETCLK = 0x06,
IOCTL_SENDCMD = 0x07, IOCTL_SENDCMD = 0x07,
IOCTL_GETSTATUS = 0x0B, IOCTL_GETSTATUS = 0x0B,
IOCTL_GETOCR = 0x0C, IOCTL_GETOCR = 0x0C,
}; };
// IOCtlV // IOCtlV
enum enum
{ {
IOCTLV_SENDCMD = 0x07, IOCTLV_SENDCMD = 0x07,
}; };
// ExecuteCommand // ExecuteCommand
@ -63,33 +63,33 @@ private:
// Status // Status
enum enum
{ {
CARD_NOT_EXIST = 0, CARD_NOT_EXIST = 0,
CARD_INSERTED = 1, CARD_INSERTED = 1,
CARD_INITIALIZED = 0x10000, CARD_INITIALIZED = 0x10000,
}; };
// Commands // Commands
enum enum
{ {
GO_IDLE_STATE = 0x00, GO_IDLE_STATE = 0x00,
ALL_SEND_CID = 0x02, ALL_SEND_CID = 0x02,
SEND_RELATIVE_ADDR = 0x03, SEND_RELATIVE_ADDR = 0x03,
SELECT_CARD = 0x07, SELECT_CARD = 0x07,
SEND_IF_COND = 0x08, SEND_IF_COND = 0x08,
SEND_CSD = 0x09, SEND_CSD = 0x09,
SEND_CID = 0x0A, SEND_CID = 0x0A,
SEND_STATUS = 0x0D, SEND_STATUS = 0x0D,
SET_BLOCKLEN = 0x10, SET_BLOCKLEN = 0x10,
READ_MULTIPLE_BLOCK = 0x12, READ_MULTIPLE_BLOCK = 0x12,
WRITE_MULTIPLE_BLOCK= 0x19, WRITE_MULTIPLE_BLOCK = 0x19,
APP_CMD_NEXT = 0x37, APP_CMD_NEXT = 0x37,
ACMD_SETBUSWIDTH = 0x06, ACMD_SETBUSWIDTH = 0x06,
ACMD_SENDOPCOND = 0x29, ACMD_SENDOPCOND = 0x29,
ACMD_SENDSCR = 0x33, ACMD_SENDSCR = 0x33,
EVENT_REGISTER = 0x40, EVENT_REGISTER = 0x40,
EVENT_UNREGISTER = 0x41, EVENT_UNREGISTER = 0x41,
}; };
enum EventType enum EventType

14
Source/Core/Core/IPC_HLE/WII_IPC_HLE_Device_usb.h
View File

@ -76,17 +76,17 @@ public:
private: private:
enum USBIOCtl enum USBIOCtl
{ {
USBV0_IOCTL_CTRLMSG = 0, USBV0_IOCTL_CTRLMSG = 0,
USBV0_IOCTL_BLKMSG = 1, USBV0_IOCTL_BLKMSG = 1,
USBV0_IOCTL_INTRMSG = 2, USBV0_IOCTL_INTRMSG = 2,
}; };
enum USBEndpoint enum USBEndpoint
{ {
HCI_CTRL = 0x00, HCI_CTRL = 0x00,
HCI_EVENT = 0x81, HCI_EVENT = 0x81,
ACL_DATA_IN = 0x82, ACL_DATA_IN = 0x82,
ACL_DATA_OUT = 0x02 ACL_DATA_OUT = 0x02
}; };
struct SHCICommandMessage struct SHCICommandMessage

8
Source/Core/Core/IPC_HLE/WII_IPC_HLE_Device_usb_kbd.h
View File

@ -20,9 +20,9 @@ public:
private: private:
enum enum
{ {
MSG_KBD_CONNECT = 0, MSG_KBD_CONNECT = 0,
MSG_KBD_DISCONNECT, MSG_KBD_DISCONNECT = 1,
MSG_EVENT MSG_EVENT = 2
}; };
#pragma pack(push, 1) #pragma pack(push, 1)
@ -58,7 +58,7 @@ private:
enum enum
{ {
KBD_LAYOUT_QWERTY = 0, KBD_LAYOUT_QWERTY = 0,
KBD_LAYOUT_AZERTY KBD_LAYOUT_AZERTY = 1
}; };
int m_KeyboardLayout; int m_KeyboardLayout;
static u8 m_KeyCodesQWERTY[256]; static u8 m_KeyCodesQWERTY[256];

12
Source/Core/Core/IPC_HLE/WII_Socket.h
View File

@ -53,8 +53,8 @@ typedef struct pollfd pollfd_t;
#include "WII_IPC_HLE_Device_net_ssl.h" #include "WII_IPC_HLE_Device_net_ssl.h"
enum { enum {
SO_MSG_OOB = 0x01, SO_MSG_OOB = 0x01,
SO_MSG_PEEK = 0x02, SO_MSG_PEEK = 0x02,
SO_MSG_NONBLOCK = 0x04, SO_MSG_NONBLOCK = 0x04,
}; };
enum { enum {
@ -154,10 +154,10 @@ struct WiiSockAddr
struct WiiSockAddrIn struct WiiSockAddrIn
{ {
u8 len; u8 len;
u8 family; u8 family;
u16 port; u16 port;
WiiInAddr addr; WiiInAddr addr;
}; };
#pragma pack(pop) #pragma pack(pop)

40
Source/Core/Core/NetPlayProto.h
View File

@ -36,29 +36,29 @@ const int NETPLAY_INITIAL_GCTIME = 1272737767;
// messages // messages
enum enum
{ {
NP_MSG_PLAYER_JOIN = 0x10, NP_MSG_PLAYER_JOIN = 0x10,
NP_MSG_PLAYER_LEAVE = 0x11, NP_MSG_PLAYER_LEAVE = 0x11,
NP_MSG_CHAT_MESSAGE = 0x30, NP_MSG_CHAT_MESSAGE = 0x30,
NP_MSG_PAD_DATA = 0x60, NP_MSG_PAD_DATA = 0x60,
NP_MSG_PAD_MAPPING = 0x61, NP_MSG_PAD_MAPPING = 0x61,
NP_MSG_PAD_BUFFER = 0x62, NP_MSG_PAD_BUFFER = 0x62,
NP_MSG_WIIMOTE_DATA = 0x70, NP_MSG_WIIMOTE_DATA = 0x70,
NP_MSG_WIIMOTE_MAPPING = 0x71, NP_MSG_WIIMOTE_MAPPING = 0x71,
NP_MSG_START_GAME = 0xA0, NP_MSG_START_GAME = 0xA0,
NP_MSG_CHANGE_GAME = 0xA1, NP_MSG_CHANGE_GAME = 0xA1,
NP_MSG_STOP_GAME = 0xA2, NP_MSG_STOP_GAME = 0xA2,
NP_MSG_DISABLE_GAME = 0xA3, NP_MSG_DISABLE_GAME = 0xA3,
NP_MSG_READY = 0xD0, NP_MSG_READY = 0xD0,
NP_MSG_NOT_READY = 0xD1, NP_MSG_NOT_READY = 0xD1,
NP_MSG_PING = 0xE0, NP_MSG_PING = 0xE0,
NP_MSG_PONG = 0xE1, NP_MSG_PONG = 0xE1,
NP_MSG_PLAYER_PING_DATA = 0xE2, NP_MSG_PLAYER_PING_DATA = 0xE2,
}; };
typedef u8 MessageId; typedef u8 MessageId;
@ -68,9 +68,9 @@ typedef u32 FrameNum;
enum enum
{ {
CON_ERR_SERVER_FULL = 1, CON_ERR_SERVER_FULL = 1,
CON_ERR_GAME_RUNNING, CON_ERR_GAME_RUNNING = 2,
CON_ERR_VERSION_MISMATCH CON_ERR_VERSION_MISMATCH = 3
}; };
namespace NetPlay { namespace NetPlay {

18
Source/Core/Core/PowerPC/Gekko.h
View File

@ -695,20 +695,20 @@ union UReg_PTE
// quantize types // quantize types
enum EQuantizeType enum EQuantizeType
{ {
QUANTIZE_FLOAT = 0, QUANTIZE_FLOAT = 0,
QUANTIZE_U8 = 4, QUANTIZE_U8 = 4,
QUANTIZE_U16 = 5, QUANTIZE_U16 = 5,
QUANTIZE_S8 = 6, QUANTIZE_S8 = 6,
QUANTIZE_S16 = 7, QUANTIZE_S16 = 7,
}; };
// branches // branches
enum enum
{ {
BO_BRANCH_IF_CTR_0 = 2, // 3 BO_BRANCH_IF_CTR_0 = 2, // 3
BO_DONT_DECREMENT_FLAG = 4, // 2 BO_DONT_DECREMENT_FLAG = 4, // 2
BO_BRANCH_IF_TRUE = 8, // 1 BO_BRANCH_IF_TRUE = 8, // 1
BO_DONT_CHECK_CONDITION = 16, // 0 BO_DONT_CHECK_CONDITION = 16, // 0
}; };
// Special purpose register indices // Special purpose register indices

67
Source/Core/Core/PowerPC/PPCTables.h
View File

@ -10,33 +10,33 @@
enum enum
{ {
FL_SET_CR0 = (1<<0), // FL_SET_CR0 = (1<<0), //
FL_SET_CR1 = (1<<1), // FL_SET_CR1 = (1<<1), //
FL_SET_CRn = (1<<2), // FL_SET_CRn = (1<<2), //
FL_SET_CRx = FL_SET_CR0 | FL_SET_CR1 | FL_SET_CRn, // FL_SET_CRx = FL_SET_CR0 | FL_SET_CR1 | FL_SET_CRn, //
FL_SET_CA = (1<<3), // carry FL_SET_CA = (1<<3), // carry
FL_READ_CA = (1<<4), // carry FL_READ_CA = (1<<4), // carry
FL_RC_BIT = (1<<5), FL_RC_BIT = (1<<5),
FL_RC_BIT_F = (1<<6), FL_RC_BIT_F = (1<<6),
FL_ENDBLOCK = (1<<7), FL_ENDBLOCK = (1<<7),
FL_IN_A = (1<<8), FL_IN_A = (1<<8),
FL_IN_A0 = (1<<9), FL_IN_A0 = (1<<9),
FL_IN_B = (1<<10), FL_IN_B = (1<<10),
FL_IN_C = (1<<11), FL_IN_C = (1<<11),
FL_IN_S = (1<<12), FL_IN_S = (1<<12),
FL_IN_AB = FL_IN_A | FL_IN_B, FL_IN_AB = FL_IN_A | FL_IN_B,
FL_IN_SB = FL_IN_S | FL_IN_B, FL_IN_SB = FL_IN_S | FL_IN_B,
FL_IN_A0B = FL_IN_A0 | FL_IN_B, FL_IN_A0B = FL_IN_A0 | FL_IN_B,
FL_IN_A0BC = FL_IN_A0 | FL_IN_B | FL_IN_C, FL_IN_A0BC = FL_IN_A0 | FL_IN_B | FL_IN_C,
FL_OUT_D = (1<<13), FL_OUT_D = (1<<13),
FL_OUT_S = FL_OUT_D, FL_OUT_S = FL_OUT_D,
FL_OUT_A = (1<<14), FL_OUT_A = (1<<14),
FL_OUT_AD = FL_OUT_A | FL_OUT_D, FL_OUT_AD = FL_OUT_A | FL_OUT_D,
FL_TIMER = (1<<15), FL_TIMER = (1<<15),
FL_CHECKEXCEPTIONS = (1<<16), FL_CHECKEXCEPTIONS = (1<<16),
FL_EVIL = (1<<17), FL_EVIL = (1<<17),
FL_USE_FPU = (1<<18), FL_USE_FPU = (1<<18),
FL_LOADSTORE = (1<<19), FL_LOADSTORE = (1<<19),
}; };
enum enum
@ -60,17 +60,20 @@ enum
OPTYPE_UNKNOWN , OPTYPE_UNKNOWN ,
}; };
enum { enum
OPCD_HLEFUNCTION = 1, {
OPCD_HLEFUNCTION = 1,
OPCD_COMPILEDBLOCK = 2, OPCD_COMPILEDBLOCK = 2,
OPCD_BCx = 16, OPCD_BCx = 16,
OPCD_SC = 17, OPCD_SC = 17,
OPCD_Bx = 18, OPCD_Bx = 18,
}; };
enum { enum
{
OP_BLR = 0x4e800020, OP_BLR = 0x4e800020,
}; };
struct GekkoOPInfo struct GekkoOPInfo
{ {
const char *opname; const char *opname;

2
Source/Core/DiscIO/BannerLoaderWii.h
View File

@ -31,7 +31,7 @@ class CBannerLoaderWii
enum enum
{ {
TEXTURE_SIZE = 192 * 64 * 2, TEXTURE_SIZE = 192 * 64 * 2,
ICON_SIZE = 48 * 48 * 2, ICON_SIZE = 48 * 48 * 2,
COMMENT_SIZE = 32 COMMENT_SIZE = 32
}; };

6
Source/Core/DiscIO/NANDContentLoader.h
View File

@ -59,10 +59,10 @@ public:
enum enum
{ {
TMD_VIEW_SIZE = 0x58, TMD_VIEW_SIZE = 0x58,
TMD_HEADER_SIZE = 0x1e4, TMD_HEADER_SIZE = 0x1E4,
CONTENT_HEADER_SIZE = 0x24, CONTENT_HEADER_SIZE = 0x24,
TICKET_SIZE = 0x2A4 TICKET_SIZE = 0x2A4
}; };
}; };

28
Source/Core/DolphinWX/MemoryCards/WiiSaveCrypted.h
View File

@ -56,21 +56,21 @@ private:
enum enum
{ {
BLOCK_SZ = 0x40, BLOCK_SZ = 0x40,
HDR_SZ = 0x20, HDR_SZ = 0x20,
ICON_SZ = 0x1200, ICON_SZ = 0x1200,
BNR_SZ = 0x60a0, BNR_SZ = 0x60a0,
FULL_BNR_MIN = 0x72a0, // BNR_SZ + 1*ICON_SZ FULL_BNR_MIN = 0x72a0, // BNR_SZ + 1*ICON_SZ
FULL_BNR_MAX = 0xF0A0, // BNR_SZ + 8*ICON_SZ FULL_BNR_MAX = 0xF0A0, // BNR_SZ + 8*ICON_SZ
HEADER_SZ = 0xF0C0, // HDR_SZ + FULL_BNR_MAX HEADER_SZ = 0xF0C0, // HDR_SZ + FULL_BNR_MAX
BK_LISTED_SZ = 0x70, // Size before rounding to nearest block BK_LISTED_SZ = 0x70, // Size before rounding to nearest block
BK_SZ = 0x80, BK_SZ = 0x80,
FILE_HDR_SZ = 0x80, FILE_HDR_SZ = 0x80,
SIG_SZ = 0x40, SIG_SZ = 0x40,
NG_CERT_SZ = 0x180, NG_CERT_SZ = 0x180,
AP_CERT_SZ = 0x180, AP_CERT_SZ = 0x180,
FULL_CERT_SZ = 0x3C0, // SIG_SZ + NG_CERT_SZ + AP_CERT_SZ + 0x80? FULL_CERT_SZ = 0x3C0, // SIG_SZ + NG_CERT_SZ + AP_CERT_SZ + 0x80?
BK_HDR_MAGIC = 0x426B0001, BK_HDR_MAGIC = 0x426B0001,
FILE_HDR_MAGIC = 0x03adf17e FILE_HDR_MAGIC = 0x03adf17e

4
Source/Core/VideoBackends/Software/RasterFont.h
View File

@ -13,8 +13,8 @@ public:
static int debug; static int debug;
// some useful constants // some useful constants
enum {char_width = 10}; enum {char_width = 10};
enum {char_height = 15}; enum {char_height = 15};
// and the happy helper functions // and the happy helper functions
void printString(const char *s, double x, double y, double z=0.0); void printString(const char *s, double x, double y, double z=0.0);

48
Source/Core/VideoBackends/Software/SWCommandProcessor.h
View File

@ -17,30 +17,30 @@ namespace SWCommandProcessor
// internal hardware addresses // internal hardware addresses
enum enum
{ {
STATUS_REGISTER = 0x00, STATUS_REGISTER = 0x00,
CTRL_REGISTER = 0x02, CTRL_REGISTER = 0x02,
CLEAR_REGISTER = 0x04, CLEAR_REGISTER = 0x04,
FIFO_TOKEN_REGISTER = 0x0E, FIFO_TOKEN_REGISTER = 0x0E,
FIFO_BOUNDING_BOX_LEFT = 0x10, FIFO_BOUNDING_BOX_LEFT = 0x10,
FIFO_BOUNDING_BOX_RIGHT = 0x12, FIFO_BOUNDING_BOX_RIGHT = 0x12,
FIFO_BOUNDING_BOX_TOP = 0x14, FIFO_BOUNDING_BOX_TOP = 0x14,
FIFO_BOUNDING_BOX_BOTTOM = 0x16, FIFO_BOUNDING_BOX_BOTTOM = 0x16,
FIFO_BASE_LO = 0x20, FIFO_BASE_LO = 0x20,
FIFO_BASE_HI = 0x22, FIFO_BASE_HI = 0x22,
FIFO_END_LO = 0x24, FIFO_END_LO = 0x24,
FIFO_END_HI = 0x26, FIFO_END_HI = 0x26,
FIFO_HI_WATERMARK_LO = 0x28, FIFO_HI_WATERMARK_LO = 0x28,
FIFO_HI_WATERMARK_HI = 0x2a, FIFO_HI_WATERMARK_HI = 0x2a,
FIFO_LO_WATERMARK_LO = 0x2c, FIFO_LO_WATERMARK_LO = 0x2c,
FIFO_LO_WATERMARK_HI = 0x2e, FIFO_LO_WATERMARK_HI = 0x2e,
FIFO_RW_DISTANCE_LO = 0x30, FIFO_RW_DISTANCE_LO = 0x30,
FIFO_RW_DISTANCE_HI = 0x32, FIFO_RW_DISTANCE_HI = 0x32,
FIFO_WRITE_POINTER_LO = 0x34, FIFO_WRITE_POINTER_LO = 0x34,
FIFO_WRITE_POINTER_HI = 0x36, FIFO_WRITE_POINTER_HI = 0x36,
FIFO_READ_POINTER_LO = 0x38, FIFO_READ_POINTER_LO = 0x38,
FIFO_READ_POINTER_HI = 0x3A, FIFO_READ_POINTER_HI = 0x3A,
FIFO_BP_LO = 0x3C, FIFO_BP_LO = 0x3C,
FIFO_BP_HI = 0x3E FIFO_BP_HI = 0x3E
}; };
// Fifo Status Register // Fifo Status Register

4
Source/Core/VideoBackends/Software/SWPixelEngine.cpp
View File

@ -22,8 +22,8 @@ namespace SWPixelEngine
enum enum
{ {
INT_CAUSE_PE_TOKEN = 0x200, // GP Token INT_CAUSE_PE_TOKEN = 0x200, // GP Token
INT_CAUSE_PE_FINISH = 0x400, // GP Finished INT_CAUSE_PE_FINISH = 0x400, // GP Finished
}; };
// STATE_TO_SAVE // STATE_TO_SAVE

18
Source/Core/VideoBackends/Software/SWPixelEngine.h
View File

@ -15,17 +15,17 @@ namespace SWPixelEngine
// internal hardware addresses // internal hardware addresses
enum enum
{ {
PE_ZCONF = 0x000, // Z Config PE_ZCONF = 0x000, // Z Config
PE_ALPHACONF = 0x002, // Alpha Config PE_ALPHACONF = 0x002, // Alpha Config
PE_DSTALPHACONF = 0x004, // Destination Alpha Config PE_DSTALPHACONF = 0x004, // Destination Alpha Config
PE_ALPHAMODE = 0x006, // Alpha Mode Config PE_ALPHAMODE = 0x006, // Alpha Mode Config
PE_ALPHAREAD = 0x008, // Alpha Read PE_ALPHAREAD = 0x008, // Alpha Read
PE_CTRL_REGISTER = 0x00a, // Control PE_CTRL_REGISTER = 0x00a, // Control
PE_TOKEN_REG = 0x00e, // Token PE_TOKEN_REG = 0x00e, // Token
PE_BBOX_LEFT = 0x010, // Flip Left PE_BBOX_LEFT = 0x010, // Flip Left
PE_BBOX_RIGHT = 0x012, // Flip Right PE_BBOX_RIGHT = 0x012, // Flip Right
PE_BBOX_TOP = 0x014, // Flip Top PE_BBOX_TOP = 0x014, // Flip Top
PE_BBOX_BOTTOM = 0x016, // Flip Bottom PE_BBOX_BOTTOM = 0x016, // Flip Bottom
// NOTE: Order not verified // NOTE: Order not verified
// These indicate the number of quads that are being used as input/output for each particular stage // These indicate the number of quads that are being used as input/output for each particular stage

38
Source/Core/VideoCommon/CPMemory.h
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@ -10,39 +10,39 @@
// Vertex array numbers // Vertex array numbers
enum enum
{ {
ARRAY_POSITION = 0, ARRAY_POSITION = 0,
ARRAY_NORMAL = 1, ARRAY_NORMAL = 1,
ARRAY_COLOR = 2, ARRAY_COLOR = 2,
ARRAY_COLOR2 = 3, ARRAY_COLOR2 = 3,
ARRAY_TEXCOORD0 = 4, ARRAY_TEXCOORD0 = 4,
}; };
// Vertex components // Vertex components
enum enum
{ {
NOT_PRESENT = 0, NOT_PRESENT = 0,
DIRECT = 1, DIRECT = 1,
INDEX8 = 2, INDEX8 = 2,
INDEX16 = 3, INDEX16 = 3,
}; };
enum enum
{ {
FORMAT_UBYTE = 0, // 2 Cmp FORMAT_UBYTE = 0, // 2 Cmp
FORMAT_BYTE = 1, // 3 Cmp FORMAT_BYTE = 1, // 3 Cmp
FORMAT_USHORT = 2, FORMAT_USHORT = 2,
FORMAT_SHORT = 3, FORMAT_SHORT = 3,
FORMAT_FLOAT = 4, FORMAT_FLOAT = 4,
}; };
enum enum
{ {
FORMAT_16B_565 = 0, // NA FORMAT_16B_565 = 0, // NA
FORMAT_24B_888 = 1, FORMAT_24B_888 = 1,
FORMAT_32B_888x = 2, FORMAT_32B_888x = 2,
FORMAT_16B_4444 = 3, FORMAT_16B_4444 = 3,
FORMAT_24B_6666 = 4, FORMAT_24B_6666 = 4,
FORMAT_32B_8888 = 5, FORMAT_32B_8888 = 5,
}; };
enum enum

84
Source/Core/VideoCommon/CommandProcessor.h
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@ -27,48 +27,48 @@ extern volatile bool interruptFinishWaiting;
// internal hardware addresses // internal hardware addresses
enum enum
{ {
STATUS_REGISTER = 0x00, STATUS_REGISTER = 0x00,
CTRL_REGISTER = 0x02, CTRL_REGISTER = 0x02,
CLEAR_REGISTER = 0x04, CLEAR_REGISTER = 0x04,
PERF_SELECT = 0x06, PERF_SELECT = 0x06,
FIFO_TOKEN_REGISTER = 0x0E, FIFO_TOKEN_REGISTER = 0x0E,
FIFO_BOUNDING_BOX_LEFT = 0x10, FIFO_BOUNDING_BOX_LEFT = 0x10,
FIFO_BOUNDING_BOX_RIGHT = 0x12, FIFO_BOUNDING_BOX_RIGHT = 0x12,
FIFO_BOUNDING_BOX_TOP = 0x14, FIFO_BOUNDING_BOX_TOP = 0x14,
FIFO_BOUNDING_BOX_BOTTOM = 0x16, FIFO_BOUNDING_BOX_BOTTOM = 0x16,
FIFO_BASE_LO = 0x20, FIFO_BASE_LO = 0x20,
FIFO_BASE_HI = 0x22, FIFO_BASE_HI = 0x22,
FIFO_END_LO = 0x24, FIFO_END_LO = 0x24,
FIFO_END_HI = 0x26, FIFO_END_HI = 0x26,
FIFO_HI_WATERMARK_LO = 0x28, FIFO_HI_WATERMARK_LO = 0x28,
FIFO_HI_WATERMARK_HI = 0x2a, FIFO_HI_WATERMARK_HI = 0x2a,
FIFO_LO_WATERMARK_LO = 0x2c, FIFO_LO_WATERMARK_LO = 0x2c,
FIFO_LO_WATERMARK_HI = 0x2e, FIFO_LO_WATERMARK_HI = 0x2e,
FIFO_RW_DISTANCE_LO = 0x30, FIFO_RW_DISTANCE_LO = 0x30,
FIFO_RW_DISTANCE_HI = 0x32, FIFO_RW_DISTANCE_HI = 0x32,
FIFO_WRITE_POINTER_LO = 0x34, FIFO_WRITE_POINTER_LO = 0x34,
FIFO_WRITE_POINTER_HI = 0x36, FIFO_WRITE_POINTER_HI = 0x36,
FIFO_READ_POINTER_LO = 0x38, FIFO_READ_POINTER_LO = 0x38,
FIFO_READ_POINTER_HI = 0x3A, FIFO_READ_POINTER_HI = 0x3A,
FIFO_BP_LO = 0x3C, FIFO_BP_LO = 0x3C,
FIFO_BP_HI = 0x3E, FIFO_BP_HI = 0x3E,
XF_RASBUSY_L = 0x40, XF_RASBUSY_L = 0x40,
XF_RASBUSY_H = 0x42, XF_RASBUSY_H = 0x42,
XF_CLKS_L = 0x44, XF_CLKS_L = 0x44,
XF_CLKS_H = 0x46, XF_CLKS_H = 0x46,
XF_WAIT_IN_L = 0x48, XF_WAIT_IN_L = 0x48,
XF_WAIT_IN_H = 0x4a, XF_WAIT_IN_H = 0x4a,
XF_WAIT_OUT_L = 0x4c, XF_WAIT_OUT_L = 0x4c,
XF_WAIT_OUT_H = 0x4e, XF_WAIT_OUT_H = 0x4e,
VCACHE_METRIC_CHECK_L = 0x50, VCACHE_METRIC_CHECK_L = 0x50,
VCACHE_METRIC_CHECK_H = 0x52, VCACHE_METRIC_CHECK_H = 0x52,
VCACHE_METRIC_MISS_L = 0x54, VCACHE_METRIC_MISS_L = 0x54,
VCACHE_METRIC_MISS_H = 0x56, VCACHE_METRIC_MISS_H = 0x56,
VCACHE_METRIC_STALL_L = 0x58, VCACHE_METRIC_STALL_L = 0x58,
VCACHE_METRIC_STALL_H = 0x5A, VCACHE_METRIC_STALL_H = 0x5A,
CLKS_PER_VTX_IN_L = 0x60, CLKS_PER_VTX_IN_L = 0x60,
CLKS_PER_VTX_IN_H = 0x62, CLKS_PER_VTX_IN_H = 0x62,
CLKS_PER_VTX_OUT = 0x64, CLKS_PER_VTX_OUT = 0x64,
}; };
enum enum

32
Source/Core/VideoCommon/Debugger.h
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@ -27,27 +27,27 @@ public:
}; };
enum PauseEvent { enum PauseEvent {
NOT_PAUSE = 0, NOT_PAUSE = 0,
NEXT_FRAME = 1<<0, NEXT_FRAME = 1<<0,
NEXT_FLUSH = 1<<1, NEXT_FLUSH = 1<<1,
NEXT_PIXEL_SHADER_CHANGE = 1<<2, NEXT_PIXEL_SHADER_CHANGE = 1<<2,
NEXT_VERTEX_SHADER_CHANGE = 1<<3, NEXT_VERTEX_SHADER_CHANGE = 1<<3,
NEXT_TEXTURE_CHANGE = 1<<4, NEXT_TEXTURE_CHANGE = 1<<4,
NEXT_NEW_TEXTURE = 1<<5, NEXT_NEW_TEXTURE = 1<<5,
NEXT_XFB_CMD = 1<<6, // TODO NEXT_XFB_CMD = 1<<6, // TODO
NEXT_EFB_CMD = 1<<7, // TODO NEXT_EFB_CMD = 1<<7, // TODO
NEXT_MATRIX_CMD = 1<<8, // TODO NEXT_MATRIX_CMD = 1<<8, // TODO
NEXT_VERTEX_CMD = 1<<9, // TODO NEXT_VERTEX_CMD = 1<<9, // TODO
NEXT_TEXTURE_CMD = 1<<10, // TODO NEXT_TEXTURE_CMD = 1<<10, // TODO
NEXT_LIGHT_CMD = 1<<11, // TODO NEXT_LIGHT_CMD = 1<<11, // TODO
NEXT_FOG_CMD = 1<<12, // TODO NEXT_FOG_CMD = 1<<12, // TODO
NEXT_SET_TLUT = 1<<13, // TODO NEXT_SET_TLUT = 1<<13, // TODO
NEXT_ERROR = 1<<14, // TODO NEXT_ERROR = 1<<14, // TODO
}; };
extern GFXDebuggerBase *g_pdebugger; extern GFXDebuggerBase *g_pdebugger;

32
Source/Core/VideoCommon/DriverDetails.h
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@ -9,10 +9,10 @@ namespace DriverDetails
// Enum of supported operating systems // Enum of supported operating systems
enum OS enum OS
{ {
OS_ALL = (1 << 0), OS_ALL = (1 << 0),
OS_WINDOWS = (1 << 1), OS_WINDOWS = (1 << 1),
OS_LINUX = (1 << 2), OS_LINUX = (1 << 2),
OS_OSX = (1 << 3), OS_OSX = (1 << 3),
OS_ANDROID = (1 << 4), OS_ANDROID = (1 << 4),
}; };
// Enum of known vendors // Enum of known vendors
@ -36,21 +36,21 @@ namespace DriverDetails
enum Driver enum Driver
{ {
DRIVER_ALL = 0, DRIVER_ALL = 0,
DRIVER_NVIDIA, // Official Nvidia, including mobile GPU DRIVER_NVIDIA, // Official Nvidia, including mobile GPU
DRIVER_NOUVEAU, // OSS nouveau DRIVER_NOUVEAU, // OSS nouveau
DRIVER_ATI, // Official ATI DRIVER_ATI, // Official ATI
DRIVER_R600, // OSS Radeon DRIVER_R600, // OSS Radeon
DRIVER_INTEL, // Official Intel DRIVER_INTEL, // Official Intel
DRIVER_I965, // OSS Intel DRIVER_I965, // OSS Intel
DRIVER_ARM_4XX, // Official Mali driver DRIVER_ARM_4XX, // Official Mali driver
DRIVER_ARM_T6XX, // Official Mali driver DRIVER_ARM_T6XX, // Official Mali driver
DRIVER_LIMA, // OSS Mali driver DRIVER_LIMA, // OSS Mali driver
DRIVER_QUALCOMM_3XX, // Official Adreno driver 3xx DRIVER_QUALCOMM_3XX, // Official Adreno driver 3xx
DRIVER_QUALCOMM_2XX, // Official Adreno driver 2xx DRIVER_QUALCOMM_2XX, // Official Adreno driver 2xx
DRIVER_FREEDRENO, // OSS Adreno driver DRIVER_FREEDRENO, // OSS Adreno driver
DRIVER_IMGTEC, // OSS PowerVR driver DRIVER_IMGTEC, // OSS PowerVR driver
DRIVER_VIVANTE, // Official vivante driver DRIVER_VIVANTE, // Official vivante driver
DRIVER_UNKNOWN // Unknown driver, default to official hardware driver DRIVER_UNKNOWN // Unknown driver, default to official hardware driver
}; };
// Enum of known bugs // Enum of known bugs

4
Source/Core/VideoCommon/PixelEngine.cpp
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@ -111,8 +111,8 @@ bool bbox_active;
enum enum
{ {
INT_CAUSE_PE_TOKEN = 0x200, // GP Token INT_CAUSE_PE_TOKEN = 0x200, // GP Token
INT_CAUSE_PE_FINISH = 0x400, // GP Finished INT_CAUSE_PE_FINISH = 0x400, // GP Finished
}; };
void DoState(PointerWrap &p) void DoState(PointerWrap &p)

44
Source/Core/VideoCommon/PixelEngine.h
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@ -11,32 +11,32 @@ class PointerWrap;
// internal hardware addresses // internal hardware addresses
enum enum
{ {
PE_ZCONF = 0x00, // Z Config PE_ZCONF = 0x00, // Z Config
PE_ALPHACONF = 0x02, // Alpha Config PE_ALPHACONF = 0x02, // Alpha Config
PE_DSTALPHACONF = 0x04, // Destination Alpha Config PE_DSTALPHACONF = 0x04, // Destination Alpha Config
PE_ALPHAMODE = 0x06, // Alpha Mode Config PE_ALPHAMODE = 0x06, // Alpha Mode Config
PE_ALPHAREAD = 0x08, // Alpha Read PE_ALPHAREAD = 0x08, // Alpha Read
PE_CTRL_REGISTER = 0x0a, // Control PE_CTRL_REGISTER = 0x0a, // Control
PE_TOKEN_REG = 0x0e, // Token PE_TOKEN_REG = 0x0e, // Token
PE_BBOX_LEFT = 0x10, // Flip Left PE_BBOX_LEFT = 0x10, // Flip Left
PE_BBOX_RIGHT = 0x12, // Flip Right PE_BBOX_RIGHT = 0x12, // Flip Right
PE_BBOX_TOP = 0x14, // Flip Top PE_BBOX_TOP = 0x14, // Flip Top
PE_BBOX_BOTTOM = 0x16, // Flip Bottom PE_BBOX_BOTTOM = 0x16, // Flip Bottom
// NOTE: Order not verified // NOTE: Order not verified
// These indicate the number of quads that are being used as input/output for each particular stage // These indicate the number of quads that are being used as input/output for each particular stage
PE_PERF_ZCOMP_INPUT_ZCOMPLOC_L = 0x18, PE_PERF_ZCOMP_INPUT_ZCOMPLOC_L = 0x18,
PE_PERF_ZCOMP_INPUT_ZCOMPLOC_H = 0x1a, PE_PERF_ZCOMP_INPUT_ZCOMPLOC_H = 0x1a,
PE_PERF_ZCOMP_OUTPUT_ZCOMPLOC_L = 0x1c, PE_PERF_ZCOMP_OUTPUT_ZCOMPLOC_L = 0x1c,
PE_PERF_ZCOMP_OUTPUT_ZCOMPLOC_H = 0x1e, PE_PERF_ZCOMP_OUTPUT_ZCOMPLOC_H = 0x1e,
PE_PERF_ZCOMP_INPUT_L = 0x20, PE_PERF_ZCOMP_INPUT_L = 0x20,
PE_PERF_ZCOMP_INPUT_H = 0x22, PE_PERF_ZCOMP_INPUT_H = 0x22,
PE_PERF_ZCOMP_OUTPUT_L = 0x24, PE_PERF_ZCOMP_OUTPUT_L = 0x24,
PE_PERF_ZCOMP_OUTPUT_H = 0x26, PE_PERF_ZCOMP_OUTPUT_H = 0x26,
PE_PERF_BLEND_INPUT_L = 0x28, PE_PERF_BLEND_INPUT_L = 0x28,
PE_PERF_BLEND_INPUT_H = 0x2a, PE_PERF_BLEND_INPUT_H = 0x2a,
PE_PERF_EFB_COPY_CLOCKS_L = 0x2c, PE_PERF_EFB_COPY_CLOCKS_L = 0x2c,
PE_PERF_EFB_COPY_CLOCKS_H = 0x2e, PE_PERF_EFB_COPY_CLOCKS_H = 0x2e,
}; };
namespace PixelEngine namespace PixelEngine

4
Source/Core/VideoCommon/VertexLoader.h
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@ -105,8 +105,8 @@ public:
private: private:
enum enum
{ {
NRM_ZERO = 0, NRM_ZERO = 0,
NRM_ONE = 1, NRM_ONE = 1,
NRM_THREE = 3, NRM_THREE = 3,
}; };

4
Source/Core/VideoCommon/VideoCommon.h
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@ -85,8 +85,8 @@ struct TargetRectangle : public MathUtil::Rectangle<int>
typedef enum typedef enum
{ {
API_OPENGL = 1, API_OPENGL = 1,
API_D3D = 2, API_D3D = 2,
API_NONE = 3 API_NONE = 3
} API_TYPE; } API_TYPE;
inline u32 RGBA8ToRGBA6ToRGBA8(u32 src) inline u32 RGBA8ToRGBA6ToRGBA8(u32 src)

12
Source/Core/VideoCommon/VideoConfig.h
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@ -24,14 +24,16 @@
#define CONF_SAVETARGETS 8 #define CONF_SAVETARGETS 8
#define CONF_SAVESHADERS 16 #define CONF_SAVESHADERS 16
enum AspectMode { enum AspectMode
ASPECT_AUTO = 0, {
ASPECT_AUTO = 0,
ASPECT_FORCE_16_9 = 1, ASPECT_FORCE_16_9 = 1,
ASPECT_FORCE_4_3 = 2, ASPECT_FORCE_4_3 = 2,
ASPECT_STRETCH = 3, ASPECT_STRETCH = 3,
}; };
enum EFBScale { enum EFBScale
{
SCALE_FORCE_INTEGRAL = -1, SCALE_FORCE_INTEGRAL = -1,
SCALE_AUTO, SCALE_AUTO,
SCALE_AUTO_INTEGRAL, SCALE_AUTO_INTEGRAL,