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https://github.com/dolphin-emu/dolphin.git
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DSPLLE: fix some comments, returned andc and orc (according to tests)
but andc'ls still behaves strange and we couldn't merge them together. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3915 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nakeee
parent
903346e06f
commit
45a71bf3ef
@ -94,6 +94,13 @@ void s(const UDSPInstruction& opc)
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dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
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currentEpilogeFunc = s_epi;
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}
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void s_epi(const UDSPInstruction& opc)
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{
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u8 dreg = opc.hex & 0x3;
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dsp_increment_addr_reg(dreg);
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}
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@ -108,6 +115,14 @@ void sn(const UDSPInstruction& opc)
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dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
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currentEpilogeFunc = sn_epi;
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}
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void sn_epi(const UDSPInstruction& opc)
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{
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u8 dreg = opc.hex & 0x3;
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dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]);
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}
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@ -141,9 +156,9 @@ void ln(const UDSPInstruction& opc)
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dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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}
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// LS $(0x18+D), $acS.m
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// LS $axD.l, $acS.m
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// xxxx xxxx 10dd 000s
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// Load register $(0x18+D) with value from memory pointed by register
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// Load register $axD.l with value from memory pointed by register
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// $ar0. Store value from register $acS.m to memory location pointed by
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// register $ar3. Increment both $ar0 and $ar3.
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void ls(const UDSPInstruction& opc)
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@ -165,9 +180,9 @@ void ls_epi(const UDSPInstruction& opc)
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dsp_increment_addr_reg(0x00);
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}
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// LSN $(0x18+D), $acS.m
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// LSN $acD.l, $acS.m
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// xxxx xxxx 10dd 010s
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// Load register $(0x18+D) with value from memory pointed by register
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// Load register $acD.l with value from memory pointed by register
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// $ar0. Store value from register $acS.m to memory location pointed by
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// register $ar3. Add corresponding indexing register $ix0 to addressing
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// register $ar0 and increment $ar3.
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@ -190,9 +205,9 @@ void lsn_epi(const UDSPInstruction& opc)
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dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]);
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}
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// LSM $(0x18+D), $acS.m
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// LSM $acD.l, $acS.m
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// xxxx xxxx 10dd 100s
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// Load register $(0x18+D) with value from memory pointed by register
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// Load register $acD.l with value from memory pointed by register
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// $ar0. Store value from register $acS.m to memory location pointed by
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// register $ar3. Add corresponding indexing register $ix3 to addressing
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// register $ar3 and increment $ar0.
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@ -216,9 +231,9 @@ void lsm_epi(const UDSPInstruction& opc)
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dsp_increment_addr_reg(0x00);
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}
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// LSMN $(0x18+D), $acS.m
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// LSMN $acD.l, $acS.m
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// xxxx xxxx 10dd 110s
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// Load register $(0x18+D) with value from memory pointed by register
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// Load register $acD.l with value from memory pointed by register
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// $ar0. Store value from register $acS.m to memory location pointed by
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// register $ar3. Add corresponding indexing register $ix0 to addressing
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// register $ar0 and add corresponding indexing register $ix3 to addressing
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@ -243,10 +258,10 @@ void lsnm_epi(const UDSPInstruction& opc)
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dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]);
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}
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// SL $acS.m, $(0x18+D)
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// SL $acS.m, $acD.l
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// xxxx xxxx 10dd 001s
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// Store value from register $acS.m to memory location pointed by register
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// $ar0. Load register $(0x18+D) with value from memory pointed by register
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// $ar0. Load register $acD.l with value from memory pointed by register
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// $ar3. Increment both $ar0 and $ar3.
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void sl(const UDSPInstruction& opc)
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{
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@ -267,10 +282,10 @@ void sl_epi(const UDSPInstruction& opc)
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dsp_increment_addr_reg(sreg);
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}
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// SLN $acS.m, $(0x18+D)
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// SLN $acS.m, $acD.l
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// xxxx xxxx 10dd 011s
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// Store value from register $acS.m to memory location pointed by register
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// $ar0. Load register $(0x18+D) with value from memory pointed by register
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// $ar0. Load register $acD.l with value from memory pointed by register
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// $ar3. Add corresponding indexing register $ix0 to addressing register $ar0
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// and increment $ar3.
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void sln(const UDSPInstruction& opc)
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@ -292,10 +307,10 @@ void sln_epi(const UDSPInstruction& opc)
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dsp_increment_addr_reg(sreg);
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}
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// SLM $acS.m, $(0x18+D)
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// SLM $acS.m, $acD.l
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// xxxx xxxx 10dd 101s
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// Store value from register $acS.m to memory location pointed by register
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// $ar0. Load register $(0x18+D) with value from memory pointed by register
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// $ar0. Load register $acD.l with value from memory pointed by register
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// $ar3. Add corresponding indexing register $ix3 to addressing register $ar3
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// and increment $ar0.
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void slm(const UDSPInstruction& opc)
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@ -317,10 +332,10 @@ void slm_epi(const UDSPInstruction& opc)
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dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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}
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// SLMN $acS.m, $(0x18+D)
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// SLMN $acS.m, $acD.l
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// xxxx xxxx 10dd 111s
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// Store value from register $acS.m to memory location pointed by register
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// $ar0. Load register $(0x18+D) with value from memory pointed by register
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// $ar0. Load register $acD.l with value from memory pointed by register
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// $ar3. Add corresponding indexing register $ix0 to addressing register $ar0
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// and add corresponding indexing register $ix3 to addressing register $ar3.
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void slnm(const UDSPInstruction& opc)
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@ -48,6 +48,8 @@ void sl(const UDSPInstruction& opc);
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void sln(const UDSPInstruction& opc);
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void slm(const UDSPInstruction& opc);
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void slnm(const UDSPInstruction& opc);
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void s(const UDSPInstruction& opc);
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void sn(const UDSPInstruction& opc);
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void ls_epi(const UDSPInstruction& opc);
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void lsn_epi(const UDSPInstruction& opc);
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void lsm_epi(const UDSPInstruction& opc);
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@ -56,8 +58,8 @@ void sl_epi(const UDSPInstruction& opc);
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void sln_epi(const UDSPInstruction& opc);
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void slm_epi(const UDSPInstruction& opc);
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void slnm_epi(const UDSPInstruction& opc);
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void s(const UDSPInstruction& opc);
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void sn(const UDSPInstruction& opc);
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void s_epi(const UDSPInstruction& opc);
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void sn_epi(const UDSPInstruction& opc);
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void ld(const UDSPInstruction& opc);
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void ldn(const UDSPInstruction& opc);
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void ldm(const UDSPInstruction& opc);
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@ -163,7 +163,7 @@ const DSPOPCTemplate opcodes[] =
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{"LSRN", 0x02ca, 0xffff, DSPInterpreter::lsrn, nop, 1, 0, {}, false},
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{"ASRN", 0x02cb, 0xffff, DSPInterpreter::asrn, nop, 1, 0, {}, false},
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// This one was believed to be andc'ls. Weird.
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// andc'ls is behaving weird so it got its own opcode
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{"LSRNR", 0x3d80, 0xfdff, DSPInterpreter::lsrnr, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, false},
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{"LRI", 0x0080, 0xffe0, DSPInterpreter::lri, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}}, false},
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@ -220,90 +220,92 @@ const DSPOPCTemplate opcodes[] =
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// opcodes that can be extended
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// extended opcodes, note size of opcode will be set to 0
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{"ANDC", 0x3c00, 0xfe80, DSPInterpreter::andc, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true},
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{"ORC", 0x3e00, 0xfe80, DSPInterpreter::orc, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true},
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{"NX", 0x8000, 0xf700, DSPInterpreter::nx, nop, 1 | P_EXT, 0, {}, true},
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{"M2", 0x8a00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"M0", 0x8b00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"M2", 0x8a00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"M0", 0x8b00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"CLR15", 0x8c00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"SET15", 0x8d00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"CLR15", 0x8c00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"SET15", 0x8d00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"SET16", 0x8e00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"SET40", 0x8f00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"SET16", 0x8e00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"SET40", 0x8f00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"INCM", 0x7400, 0xfeff, DSPInterpreter::incm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true},
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{"INC", 0x7600, 0xfeff, DSPInterpreter::inc, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"DECM", 0x7800, 0xfeff, DSPInterpreter::decm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true},
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{"DEC", 0x7a00, 0xfeff, DSPInterpreter::dec, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"NEG", 0x7c00, 0xfeff, DSPInterpreter::neg, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MOVNP", 0x7e00, 0xfeff, DSPInterpreter::movnp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"INCM", 0x7400, 0xfe00, DSPInterpreter::incm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true},
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{"INC", 0x7600, 0xfe00, DSPInterpreter::inc, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"DECM", 0x7800, 0xfe00, DSPInterpreter::decm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true},
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{"DEC", 0x7a00, 0xfe00, DSPInterpreter::dec, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"NEG", 0x7c00, 0xfe00, DSPInterpreter::neg, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MOVNP", 0x7e00, 0xfe00, DSPInterpreter::movnp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"TST", 0xb100, 0xf7ff, DSPInterpreter::tst, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
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{"TST", 0xb100, 0xf700, DSPInterpreter::tst, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
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// Definitely not TSTAXL, it affects one of the accumulators. (a100 or a900, same op, one parameter).
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{"TSTAXL", 0xa100, 0xffff, DSPInterpreter::tstaxl, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
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{"TSTAXL", 0xa100, 0xff00, DSPInterpreter::tstaxl, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
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{"TSTAXH", 0x8600, 0xfeff, DSPInterpreter::tstaxh, nop, 1 | P_EXT, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true},
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{"TSTAXH", 0x8600, 0xfe00, DSPInterpreter::tstaxh, nop, 1 | P_EXT, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true},
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{"CMP", 0x8200, 0xffff, DSPInterpreter::cmp, nop, 1 | P_EXT, 0, {}, true},
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{"CMP", 0x8200, 0xff00, DSPInterpreter::cmp, nop, 1 | P_EXT, 0, {}, true},
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// This op does NOT exist, at least not under this name, in duddie's docs!
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{"CMPAR" , 0xc100, 0xe7ff, DSPInterpreter::cmpar, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true},
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{"CMPAR" , 0xc100, 0xe700, DSPInterpreter::cmpar, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true},
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{"CLRL", 0xfc00, 0xffff, DSPInterpreter::clrl, nop, 1 | P_EXT, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true}, // clear acl0
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{"CLR", 0x8100, 0xf7ff, DSPInterpreter::clr, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, // clear acc0
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{"CLRP", 0x8400, 0xffff, DSPInterpreter::clrp, nop, 1 | P_EXT, 0, {}, },
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{"CLRL", 0xfc00, 0xff00, DSPInterpreter::clrl, nop, 1 | P_EXT, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true}, // clear acl0
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{"CLR", 0x8100, 0xf700, DSPInterpreter::clr, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, // clear acc0
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{"CLRP", 0x8400, 0xff00, DSPInterpreter::clrp, nop, 1 | P_EXT, 0, {}, },
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{"MOV", 0x6c00, 0xfeff, DSPInterpreter::mov, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true},
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{"MOVAX", 0x6800, 0xfcff, DSPInterpreter::movax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true},
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{"MOVR", 0x6000, 0xf8ff, DSPInterpreter::movr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true},
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{"MOVP", 0x6e00, 0xfeff, DSPInterpreter::movp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MOVPZ", 0xfe00, 0xfeff, DSPInterpreter::movpz, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MOV", 0x6c00, 0xfe00, DSPInterpreter::mov, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true},
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{"MOVAX", 0x6800, 0xfc00, DSPInterpreter::movax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true},
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{"MOVR", 0x6000, 0xf800, DSPInterpreter::movr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true},
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{"MOVP", 0x6e00, 0xfe00, DSPInterpreter::movp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MOVPZ", 0xfe00, 0xfe00, DSPInterpreter::movpz, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"ADDPAXZ", 0xf800, 0xfcff, DSPInterpreter::addpaxz, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_REG1A, 1, 0, 8, 0x0100}}, true}, //Think the args are wrong
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{"ADDP", 0x4e00, 0xfeff, DSPInterpreter::addp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"ADDPAXZ", 0xf800, 0xfc00, DSPInterpreter::addpaxz, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_REG1A, 1, 0, 8, 0x0100}}, true}, //Think the args are wrong
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{"ADDP", 0x4e00, 0xfe00, DSPInterpreter::addp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"LSL16", 0xf000, 0xfeff, DSPInterpreter::lsl16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"LSR16", 0xf400, 0xfeff, DSPInterpreter::lsr16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"ASR16", 0x9100, 0xf7ff, DSPInterpreter::asr16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
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{"LSL16", 0xf000, 0xfe00, DSPInterpreter::lsl16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"LSR16", 0xf400, 0xfe00, DSPInterpreter::lsr16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"ASR16", 0x9100, 0xf700, DSPInterpreter::asr16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
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{"XORR", 0x3000, 0xfcff, DSPInterpreter::xorr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true},
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{"ANDR", 0x3400, 0xfcff, DSPInterpreter::andr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true},
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{"ORR", 0x3800, 0xfcff, DSPInterpreter::orr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true},
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{"XORR", 0x3000, 0xfc00, DSPInterpreter::xorr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true},
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{"ANDR", 0x3400, 0xfc00, DSPInterpreter::andr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true},
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{"ORR", 0x3800, 0xfc00, DSPInterpreter::orr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true},
|
||||
|
||||
{"MULX", 0xa000, 0xe7ff, DSPInterpreter::mulx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true},
|
||||
{"MULXMVZ", 0xa200, 0xe6ff, DSPInterpreter::mulxmvz, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULXAC", 0xa400, 0xe6ff, DSPInterpreter::mulxac, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULXMV", 0xa600, 0xe6ff, DSPInterpreter::mulxmv, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULX", 0xa000, 0xe700, DSPInterpreter::mulx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true},
|
||||
{"MULXMVZ", 0xa200, 0xe600, DSPInterpreter::mulxmvz, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULXAC", 0xa400, 0xe600, DSPInterpreter::mulxac, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULXMV", 0xa600, 0xe600, DSPInterpreter::mulxmv, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
|
||||
{"MUL", 0x9000, 0xf7ff, DSPInterpreter::mul, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true},
|
||||
{"MULMVZ", 0x9200, 0xf6ff, DSPInterpreter::mulmvz, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULAC", 0x9400, 0xf6ff, DSPInterpreter::mulac, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULMV", 0x9600, 0xf6ff, DSPInterpreter::mulmv, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MUL", 0x9000, 0xf700, DSPInterpreter::mul, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true},
|
||||
{"MULMVZ", 0x9200, 0xf600, DSPInterpreter::mulmvz, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULAC", 0x9400, 0xf600, DSPInterpreter::mulac, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULMV", 0x9600, 0xf600, DSPInterpreter::mulmv, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
|
||||
{"MULC", 0xc000, 0xe7ff, DSPInterpreter::mulc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true},
|
||||
{"MULCMVZ", 0xc200, 0xe6ff, DSPInterpreter::mulcmvz, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULCAC", 0xc400, 0xe6ff, DSPInterpreter::mulcac, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULCMV", 0xc600, 0xe6ff, DSPInterpreter::mulcmv, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULC", 0xc000, 0xe700, DSPInterpreter::mulc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true},
|
||||
{"MULCMVZ", 0xc200, 0xe600, DSPInterpreter::mulcmvz, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULCAC", 0xc400, 0xe600, DSPInterpreter::mulcac, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MULCMV", 0xc600, 0xe600, DSPInterpreter::mulcmv, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
|
||||
{"ADDR", 0x4000, 0xf8ff, DSPInterpreter::addr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true},
|
||||
{"ADDAX", 0x4800, 0xfcff, DSPInterpreter::addax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true},
|
||||
{"ADD", 0x4c00, 0xfeff, DSPInterpreter::add, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true},
|
||||
{"ADDAXL", 0x7000, 0xfcff, DSPInterpreter::addaxl, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true},
|
||||
{"ADDR", 0x4000, 0xf800, DSPInterpreter::addr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true},
|
||||
{"ADDAX", 0x4800, 0xfc00, DSPInterpreter::addax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true},
|
||||
{"ADD", 0x4c00, 0xfe00, DSPInterpreter::add, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true},
|
||||
{"ADDAXL", 0x7000, 0xfc00, DSPInterpreter::addaxl, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true},
|
||||
|
||||
{"SUBR", 0x5000, 0xf8ff, DSPInterpreter::subr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true},
|
||||
{"SUBAX", 0x5800, 0xfcff, DSPInterpreter::subax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true},
|
||||
{"SUB", 0x5c00, 0xfeff, DSPInterpreter::sub, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true},
|
||||
{"SUBP", 0x5e00, 0xfeff, DSPInterpreter::subp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"SUBR", 0x5000, 0xf800, DSPInterpreter::subr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true},
|
||||
{"SUBAX", 0x5800, 0xfc00, DSPInterpreter::subax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true},
|
||||
{"SUB", 0x5c00, 0xfe00, DSPInterpreter::sub, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true},
|
||||
{"SUBP", 0x5e00, 0xfe00, DSPInterpreter::subp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
|
||||
{"MADD", 0xf200, 0xfeff, DSPInterpreter::madd, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true},
|
||||
{"MSUB", 0xf600, 0xfeff, DSPInterpreter::msub , nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true},
|
||||
{"MADDX", 0xe000, 0xfcff, DSPInterpreter::maddx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true},
|
||||
{"MSUBX", 0xe400, 0xfcff, DSPInterpreter::msubx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true},
|
||||
{"MADDC", 0xe800, 0xfcff, DSPInterpreter::maddc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true},
|
||||
{"MSUBC", 0xec00, 0xfcff, DSPInterpreter::msubc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true},
|
||||
{"MADD", 0xf200, 0xfe00, DSPInterpreter::madd, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true},
|
||||
{"MSUB", 0xf600, 0xfe00, DSPInterpreter::msub , nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true},
|
||||
{"MADDX", 0xe000, 0xfc00, DSPInterpreter::maddx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true},
|
||||
{"MSUBX", 0xe400, 0xfc00, DSPInterpreter::msubx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true},
|
||||
{"MADDC", 0xe800, 0xfc00, DSPInterpreter::maddc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true},
|
||||
{"MSUBC", 0xec00, 0xfc00, DSPInterpreter::msubc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true},
|
||||
};
|
||||
|
||||
const DSPOPCTemplate cw =
|
||||
@ -575,10 +577,10 @@ void InitInstructionTable()
|
||||
for (int j = 0; j < opcodes_size; j++)
|
||||
{
|
||||
u16 mask = opcodes[j].opcode_mask;
|
||||
if (opcodes[j].size & P_EXT) {
|
||||
// if (opcodes[j].size & P_EXT) {
|
||||
// Ignore extension bits.
|
||||
mask &= 0xFF00;
|
||||
}
|
||||
// mask &= 0xFF00;
|
||||
// }
|
||||
if ((mask & i) == opcodes[j].opcode)
|
||||
{
|
||||
if (opTable[i] == DSPInterpreter::unknown)
|
||||
|
||||
@ -176,7 +176,7 @@ void orr(const UDSPInstruction& opc)
|
||||
Update_SR_Register64(acc);
|
||||
}
|
||||
|
||||
/*
|
||||
// FIXME: How does it fit what we know about andc'ls
|
||||
// ANDC $acD.m, $ac(1-D).m
|
||||
// 0011 110d xxxx xxxx
|
||||
// Logic AND middle part of accumulator $acD.m with middle part of
|
||||
@ -184,31 +184,24 @@ void orr(const UDSPInstruction& opc)
|
||||
void andc(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 D = (opc.hex >> 8) & 0x1;
|
||||
g_dsp.r[DSP_REG_ACM0+D] &= dsp_get_acc_m(1-D);
|
||||
|
||||
u16 ac1 = dsp_get_acc_m(D);
|
||||
u16 ac2 = dsp_get_acc_m(1 - D);
|
||||
|
||||
dsp_set_long_acc(D, ac1 & ac2);
|
||||
|
||||
Update_SR_Register64(dsp_get_long_acc(D));
|
||||
Update_SR_Register16(dsp_get_acc_m(D));
|
||||
}
|
||||
|
||||
// FIXME: How does it fit what we know about orc'ls
|
||||
// ORC $acD.m, $ac(1-D).m
|
||||
// 0011 111d xxxx xxxx
|
||||
// Logic OR middle part of accumulator $acD.m with middle part of
|
||||
// accumulator $ax(1-D).m.
|
||||
// accumulator $ac(1-D).m.
|
||||
void orc(const UDSPInstruction& opc)
|
||||
{
|
||||
u8 D = (opc.hex >> 8) & 0x1;
|
||||
g_dsp.r[DSP_REG_ACM0+D] |= dsp_get_acc_m(1-D);
|
||||
|
||||
u16 ac1 = dsp_get_acc_m(D);
|
||||
u16 ac2 = dsp_get_acc_m(1 - D);
|
||||
|
||||
dsp_set_long_acc(D, ac1 | ac2);
|
||||
|
||||
Update_SR_Register64(dsp_get_long_acc(D));
|
||||
Update_SR_Register16(dsp_get_acc_m(D));
|
||||
}
|
||||
*/
|
||||
|
||||
void orf(const UDSPInstruction& opc)
|
||||
{
|
||||
ERROR_LOG(DSPLLE, "orf not implemented");
|
||||
|
||||
@ -9,7 +9,6 @@ files = [
|
||||
'XFStructs.cpp',
|
||||
'BPStructs.cpp',
|
||||
'memcpy_amd.cpp',
|
||||
'LookUpTables.cpp',
|
||||
'OpcodeDecoding.cpp',
|
||||
'TextureDecoder.cpp',
|
||||
'XFMemory.cpp',
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user