mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-03-12 06:39:14 +01:00
more opcode work removed CW as it makes problems, we can check for unknown instead.
to check: - TST implementation seems diffrerent from docs - CMPAR seems to cause errors in AX games (why? dis we skip clear???) - commented out for now git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2866 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nakeee
parent
36143f98b7
commit
472e67333f
@ -110,8 +110,7 @@ bool CheckCondition(u8 _Condition)
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break;
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case 0x3: // LE - LESS EQUAL
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if (g_dsp.r[R_SR] & 0x08)
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if ((g_dsp.r[R_SR] & 0x02) || (g_dsp.r[R_SR] & 0x04) || (g_dsp.r[R_SR] & 0x08))
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taken = true;
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break;
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@ -223,13 +222,11 @@ void jcc(const UDSPInstruction& opc)
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void jmprcc(const UDSPInstruction& opc)
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{
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u8 reg;
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u16 addr;
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if (CheckCondition(opc.hex & 0xf))
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{
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reg = (opc.hex >> 5) & 0x7;
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addr = dsp_op_read_reg(reg);
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g_dsp.pc = addr;
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g_dsp.pc = dsp_op_read_reg(reg);
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}
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}
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@ -477,7 +474,6 @@ void clr(const UDSPInstruction& opc)
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Update_SR_Register((s64)0);
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}
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// TODO: is this correct???
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void clrp(const UDSPInstruction& opc)
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{
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g_dsp.r[0x14] = 0x0000;
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@ -510,7 +506,6 @@ void mulcmv(const UDSPInstruction& opc)
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ERROR_LOG(DSPHLE, "dsp_opc.hex_mulcmv ni");
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}
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//TODO: add to opcode table
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void cmpar(const UDSPInstruction& opc)
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{
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u8 rreg = ((opc.hex >> 12) & 0x1) + 0x1a;
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@ -533,7 +528,6 @@ void cmp(const UDSPInstruction& opc)
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Update_SR_Register(acc0 - acc1);
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}
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//TODO: add to opcode table
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void tsta(const UDSPInstruction& opc)
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{
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u8 reg = (opc.hex >> 11) & 0x1;
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@ -557,7 +551,6 @@ void addaxl(const UDSPInstruction& opc)
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Update_SR_Register(acc);
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}
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//TODO: add to opcode table
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void addarn(const UDSPInstruction& opc)
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{
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u8 dreg = opc.hex & 0x3;
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@ -724,7 +717,6 @@ void andf(const UDSPInstruction& opc)
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}
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// FIXME inside
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// TODO: add to opcode table
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void subf(const UDSPInstruction& opc)
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{
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if (opc.hex & 0xf)
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@ -916,12 +908,21 @@ void neg(const UDSPInstruction& opc)
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Update_SR_Register(acc);
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}
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// TODO: Implement
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// FIXME: add to opcode table
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void movnp(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 8) & 0x1;
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s64 prod = dsp_get_long_prod();
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s64 acc = -prod;
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dsp_set_long_acc(dreg, acc);
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}
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// TODO: Implement
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void mov(const UDSPInstruction& opc)
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{
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// UNIMPLEMENTED
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ERROR_LOG(DSPHLE, "dsp_opc.hex_movnp\n");
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ERROR_LOG(DSPHLE, "dsp_opc.hex_mov\n");
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}
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void addax(const UDSPInstruction& opc)
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@ -1147,22 +1148,30 @@ void sbset(const UDSPInstruction& opc)
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// FIXME inside
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// TODO: add to opcode table
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void srbith(const UDSPInstruction& opc)
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{
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switch ((opc.hex >> 8) & 0xf)
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{
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case 0xa: // M2
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ERROR_LOG(DSPHLE, "dsp_opc.hex_m2\n");
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break;
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// FIXME: Both of these appear in the beginning of the Wind Waker
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case 0xb: // M0
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ERROR_LOG(DSPHLE, "dsp_opc.hex_m0\n");
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break;
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case 0xc: // CLR15
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ERROR_LOG(DSPHLE, "dsp_opc.hex_clr15\n");
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break;
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case 0xd: // SET15
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ERROR_LOG(DSPHLE, "dsp_opc.hex_set15\n");
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break;
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case 0xe: // SET40
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g_dsp.r[R_SR] &= ~(1 << 14);
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break;
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// FIXME: Both of these appear in the beginning of the Wind Waker
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//case 0xb:
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//case 0xc:
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/* case 0xf: // SET16 // that doesnt happen on a real console
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case 0xf: // SET16 // that doesnt happen on a real console
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g_dsp.r[R_SR] |= (1 << 14);
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break;*/
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break;
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default:
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break;
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@ -95,6 +95,7 @@ void dar(const UDSPInstruction& opc);
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void iar(const UDSPInstruction& opc);
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void sbclr(const UDSPInstruction& opc);
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void sbset(const UDSPInstruction& opc);
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void mov(const UDSPInstruction& opc);
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void movp(const UDSPInstruction& opc);
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void mul(const UDSPInstruction& opc);
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void mulac(const UDSPInstruction& opc);
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@ -172,7 +172,7 @@ DSPOPCTemplate opcodes[] =
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{"ORF", 0x02e0, 0xfeff, nop, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, NULL, NULL}, // Hermes: ??? (has it commented out)
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{"ADDI", 0x0200, 0xfeff, DSPInterpreter::addi, nop, 2, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},}, // F|RES: missing S64
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{"CMPI", 0x0280, 0xfeff, nop, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},}, // F|RES: missing S64
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{"SUBF", 0x0280, 0xfeff, DSPInterpreter::subf, nop, 1, 2, {{P_REG, 1, 0, 8, 0x0100}}, NULL, NULL},
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{"ILRR", 0x0210, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL},
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{"ILRRD", 0x0214, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL}, // Hermes doesn't list this
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@ -192,20 +192,19 @@ DSPOPCTemplate opcodes[] =
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{"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, nop, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_VAL, 2, 1, 0, 0xffff}}, NULL, NULL},
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{"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
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{"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_VAL, 2, 1, 0, 0xffff}}, NULL, NULL},
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{"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, nop, 2, 2, {{P_REG, 1, 0, 0, 0x00c0}, {P_REG, 2, 1, 0, 0x0003}}, NULL, NULL},
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// opcodes that can be extended
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// extended opcodes, note size of opcode will be set to 0
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{"NX", 0x8000, 0xffff, DSPInterpreter::nx, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"NX?", 0x8800, 0xffff, DSPInterpreter::nx, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"S40", 0x8e00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"S16", 0x8f00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"NX", 0x8000, 0xf700, DSPInterpreter::nx, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"M2", 0x8a00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"M0", 0x8b00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"CLR15", 0x8c00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"SET15", 0x8d00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"SET40", 0x8e00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"SET16", 0x8f00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"DECM", 0x7800, 0xfeff, DSPInterpreter::decm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"INCM", 0x7400, 0xfeff, DSPInterpreter::incm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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@ -213,21 +212,23 @@ DSPOPCTemplate opcodes[] =
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{"INC", 0x7600, 0xfeff, DSPInterpreter::inc, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"NEG", 0x7c00, 0xfeff, DSPInterpreter::neg, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"MOVNP", 0x7e00, 0xfeff, DSPInterpreter::movnp, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"TST", 0xb100, 0xf7ff, DSPInterpreter::tsta, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"TSTAXH", 0x8600, 0xfeff, DSPInterpreter::tstaxh, nop, 1 | P_EXT, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"CMP", 0x8200, 0xffff, DSPInterpreter::cmp, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"CMPAXH", 0xc100, 0xe7ff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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// {"CMPAR" , 0xc100, 0xe7ff, DSPInterpreter::cmpar, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"CLRAL0", 0xFC00, 0xffff, nop, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acl0
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{"CLRAL1", 0xFD00, 0xffff, nop, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acl1
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{"CLRAL0", 0xfc00, 0xffff, nop, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acl0
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{"CLRAL1", 0xfd00, 0xffff, nop, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acl1
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{"CLRA0", 0x8100, 0xffff, DSPInterpreter::clr, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acc0
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{"CLRA1", 0x8900, 0xffff, DSPInterpreter::clr, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acc1
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{"CLRP", 0x8400, 0xffff, DSPInterpreter::clrp, nop, 1 | P_EXT, 0, {}, },
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{"MOV", 0x6c00, 0xfeff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"MOV", 0x6c00, 0xfeff, DSPInterpreter::mov, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"MOVAX", 0x6800, 0xfcff, DSPInterpreter::movax, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"MOVR", 0x6000, 0xf8ff, DSPInterpreter::movr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"MOVP", 0x6e00, 0xfeff, DSPInterpreter::movp, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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@ -276,12 +277,6 @@ DSPOPCTemplate opcodes[] =
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{"MSUBX", 0xe400, 0xfcff, DSPInterpreter::msubx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"MADDC", 0xe800, 0xfcff, DSPInterpreter::maddc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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{"MSUBC", 0xec00, 0xfcff, DSPInterpreter::msubc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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// FIXME: nakee guessing (check masks and params!)
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{"TSTA?", 0xa100, 0xf7ff, DSPInterpreter::tsta, nop, 1 | P_EXT, 1, {{P_REG18, 1, 0, 11, 0x1000}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
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// unknown opcode for disassemble
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{"CW", 0x0000, 0x0000, nop, nop, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}}, NULL, NULL,},
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};
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DSPOPCTemplate opcodes_ext[] =
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