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more opcode work removed CW as it makes problems, we can check for unknown instead.

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to check:
- TST implementation seems diffrerent from docs
- CMPAR seems to cause errors in AX games (why? dis we skip clear???) - commented out for now




git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2866 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nakeee 2009-04-04 23:24:26 +00:00
parent 36143f98b7
commit 472e67333f
3 changed files with 41 additions and 36 deletions
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49
Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp
View File

@ -110,8 +110,7 @@ bool CheckCondition(u8 _Condition)
break; break;
case 0x3: // LE - LESS EQUAL case 0x3: // LE - LESS EQUAL
if ((g_dsp.r[R_SR] & 0x02) || (g_dsp.r[R_SR] & 0x04) || (g_dsp.r[R_SR] & 0x08))
if (g_dsp.r[R_SR] & 0x08)
taken = true; taken = true;
break; break;
@ -223,13 +222,11 @@ void jcc(const UDSPInstruction& opc)
void jmprcc(const UDSPInstruction& opc) void jmprcc(const UDSPInstruction& opc)
{ {
u8 reg; u8 reg;
u16 addr;
if (CheckCondition(opc.hex & 0xf)) if (CheckCondition(opc.hex & 0xf))
{ {
reg = (opc.hex >> 5) & 0x7; reg = (opc.hex >> 5) & 0x7;
addr = dsp_op_read_reg(reg); g_dsp.pc = dsp_op_read_reg(reg);
g_dsp.pc = addr;
} }
} }
@ -477,7 +474,6 @@ void clr(const UDSPInstruction& opc)
Update_SR_Register((s64)0); Update_SR_Register((s64)0);
} }
// TODO: is this correct???
void clrp(const UDSPInstruction& opc) void clrp(const UDSPInstruction& opc)
{ {
g_dsp.r[0x14] = 0x0000; g_dsp.r[0x14] = 0x0000;
@ -510,7 +506,6 @@ void mulcmv(const UDSPInstruction& opc)
ERROR_LOG(DSPHLE, "dsp_opc.hex_mulcmv ni"); ERROR_LOG(DSPHLE, "dsp_opc.hex_mulcmv ni");
} }
//TODO: add to opcode table
void cmpar(const UDSPInstruction& opc) void cmpar(const UDSPInstruction& opc)
{ {
u8 rreg = ((opc.hex >> 12) & 0x1) + 0x1a; u8 rreg = ((opc.hex >> 12) & 0x1) + 0x1a;
@ -533,7 +528,6 @@ void cmp(const UDSPInstruction& opc)
Update_SR_Register(acc0 - acc1); Update_SR_Register(acc0 - acc1);
} }
//TODO: add to opcode table
void tsta(const UDSPInstruction& opc) void tsta(const UDSPInstruction& opc)
{ {
u8 reg = (opc.hex >> 11) & 0x1; u8 reg = (opc.hex >> 11) & 0x1;
@ -557,7 +551,6 @@ void addaxl(const UDSPInstruction& opc)
Update_SR_Register(acc); Update_SR_Register(acc);
} }
//TODO: add to opcode table
void addarn(const UDSPInstruction& opc) void addarn(const UDSPInstruction& opc)
{ {
u8 dreg = opc.hex & 0x3; u8 dreg = opc.hex & 0x3;
@ -724,7 +717,6 @@ void andf(const UDSPInstruction& opc)
} }
// FIXME inside // FIXME inside
// TODO: add to opcode table
void subf(const UDSPInstruction& opc) void subf(const UDSPInstruction& opc)
{ {
if (opc.hex & 0xf) if (opc.hex & 0xf)
@ -916,12 +908,21 @@ void neg(const UDSPInstruction& opc)
Update_SR_Register(acc); Update_SR_Register(acc);
} }
// TODO: Implement
// FIXME: add to opcode table
void movnp(const UDSPInstruction& opc) void movnp(const UDSPInstruction& opc)
{
u8 dreg = (opc.hex >> 8) & 0x1;
s64 prod = dsp_get_long_prod();
s64 acc = -prod;
dsp_set_long_acc(dreg, acc);
}
// TODO: Implement
void mov(const UDSPInstruction& opc)
{ {
// UNIMPLEMENTED // UNIMPLEMENTED
ERROR_LOG(DSPHLE, "dsp_opc.hex_movnp\n"); ERROR_LOG(DSPHLE, "dsp_opc.hex_mov\n");
} }
void addax(const UDSPInstruction& opc) void addax(const UDSPInstruction& opc)
@ -1147,22 +1148,30 @@ void sbset(const UDSPInstruction& opc)
// FIXME inside // FIXME inside
// TODO: add to opcode table
void srbith(const UDSPInstruction& opc) void srbith(const UDSPInstruction& opc)
{ {
switch ((opc.hex >> 8) & 0xf) switch ((opc.hex >> 8) & 0xf)
{ {
case 0xa: // M2
ERROR_LOG(DSPHLE, "dsp_opc.hex_m2\n");
break;
// FIXME: Both of these appear in the beginning of the Wind Waker
case 0xb: // M0
ERROR_LOG(DSPHLE, "dsp_opc.hex_m0\n");
break;
case 0xc: // CLR15
ERROR_LOG(DSPHLE, "dsp_opc.hex_clr15\n");
break;
case 0xd: // SET15
ERROR_LOG(DSPHLE, "dsp_opc.hex_set15\n");
break;
case 0xe: // SET40 case 0xe: // SET40
g_dsp.r[R_SR] &= ~(1 << 14); g_dsp.r[R_SR] &= ~(1 << 14);
break; break;
// FIXME: Both of these appear in the beginning of the Wind Waker case 0xf: // SET16 // that doesnt happen on a real console
//case 0xb:
//case 0xc:
/* case 0xf: // SET16 // that doesnt happen on a real console
g_dsp.r[R_SR] |= (1 << 14); g_dsp.r[R_SR] |= (1 << 14);
break;*/ break;
default: default:
break; break;

1
Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.h
View File

@ -95,6 +95,7 @@ void dar(const UDSPInstruction& opc);
void iar(const UDSPInstruction& opc); void iar(const UDSPInstruction& opc);
void sbclr(const UDSPInstruction& opc); void sbclr(const UDSPInstruction& opc);
void sbset(const UDSPInstruction& opc); void sbset(const UDSPInstruction& opc);
void mov(const UDSPInstruction& opc);
void movp(const UDSPInstruction& opc); void movp(const UDSPInstruction& opc);
void mul(const UDSPInstruction& opc); void mul(const UDSPInstruction& opc);
void mulac(const UDSPInstruction& opc); void mulac(const UDSPInstruction& opc);

27
Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPTables.cpp
View File

@ -172,7 +172,7 @@ DSPOPCTemplate opcodes[] =
{"ORF", 0x02e0, 0xfeff, nop, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, NULL, NULL}, // Hermes: ??? (has it commented out) {"ORF", 0x02e0, 0xfeff, nop, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, NULL, NULL}, // Hermes: ??? (has it commented out)
{"ADDI", 0x0200, 0xfeff, DSPInterpreter::addi, nop, 2, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},}, // F|RES: missing S64 {"ADDI", 0x0200, 0xfeff, DSPInterpreter::addi, nop, 2, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},}, // F|RES: missing S64
{"CMPI", 0x0280, 0xfeff, nop, nop, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}},}, // F|RES: missing S64 {"SUBF", 0x0280, 0xfeff, DSPInterpreter::subf, nop, 1, 2, {{P_REG, 1, 0, 8, 0x0100}}, NULL, NULL},
{"ILRR", 0x0210, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL}, {"ILRR", 0x0210, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL},
{"ILRRD", 0x0214, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL}, // Hermes doesn't list this {"ILRRD", 0x0214, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL}, // Hermes doesn't list this
@ -192,20 +192,19 @@ DSPOPCTemplate opcodes[] =
{"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, nop, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_VAL, 2, 1, 0, 0xffff}}, NULL, NULL}, {"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, nop, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_VAL, 2, 1, 0, 0xffff}}, NULL, NULL},
{"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, NULL, NULL}, {"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
{"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_VAL, 2, 1, 0, 0xffff}}, NULL, NULL}, {"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_VAL, 2, 1, 0, 0xffff}}, NULL, NULL},
{"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, nop, 2, 2, {{P_REG, 1, 0, 0, 0x00c0}, {P_REG, 2, 1, 0, 0x0003}}, NULL, NULL},
// opcodes that can be extended // opcodes that can be extended
// extended opcodes, note size of opcode will be set to 0 // extended opcodes, note size of opcode will be set to 0
{"NX", 0x8000, 0xffff, DSPInterpreter::nx, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"NX", 0x8000, 0xf700, DSPInterpreter::nx, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"NX?", 0x8800, 0xffff, DSPInterpreter::nx, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"S40", 0x8e00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"S16", 0x8f00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"M2", 0x8a00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"M2", 0x8a00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"M0", 0x8b00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"M0", 0x8b00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"CLR15", 0x8c00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"CLR15", 0x8c00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"SET15", 0x8d00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"SET15", 0x8d00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"SET40", 0x8e00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"SET16", 0x8f00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"DECM", 0x7800, 0xfeff, DSPInterpreter::decm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"DECM", 0x7800, 0xfeff, DSPInterpreter::decm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"INCM", 0x7400, 0xfeff, DSPInterpreter::incm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"INCM", 0x7400, 0xfeff, DSPInterpreter::incm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
@ -213,21 +212,23 @@ DSPOPCTemplate opcodes[] =
{"INC", 0x7600, 0xfeff, DSPInterpreter::inc, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"INC", 0x7600, 0xfeff, DSPInterpreter::inc, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"NEG", 0x7c00, 0xfeff, DSPInterpreter::neg, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"NEG", 0x7c00, 0xfeff, DSPInterpreter::neg, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"MOVNP", 0x7e00, 0xfeff, DSPInterpreter::movnp, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"TST", 0xb100, 0xf7ff, DSPInterpreter::tsta, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"TST", 0xb100, 0xf7ff, DSPInterpreter::tsta, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"TSTAXH", 0x8600, 0xfeff, DSPInterpreter::tstaxh, nop, 1 | P_EXT, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"TSTAXH", 0x8600, 0xfeff, DSPInterpreter::tstaxh, nop, 1 | P_EXT, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"CMP", 0x8200, 0xffff, DSPInterpreter::cmp, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"CMP", 0x8200, 0xffff, DSPInterpreter::cmp, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"CMPAXH", 0xc100, 0xe7ff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"CLRAL0", 0xFC00, 0xffff, nop, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acl0 // {"CMPAR" , 0xc100, 0xe7ff, DSPInterpreter::cmpar, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"CLRAL1", 0xFD00, 0xffff, nop, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acl1
{"CLRAL0", 0xfc00, 0xffff, nop, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acl0
{"CLRAL1", 0xfd00, 0xffff, nop, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acl1
{"CLRA0", 0x8100, 0xffff, DSPInterpreter::clr, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acc0 {"CLRA0", 0x8100, 0xffff, DSPInterpreter::clr, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acc0
{"CLRA1", 0x8900, 0xffff, DSPInterpreter::clr, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acc1 {"CLRA1", 0x8900, 0xffff, DSPInterpreter::clr, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, // clear acc1
{"CLRP", 0x8400, 0xffff, DSPInterpreter::clrp, nop, 1 | P_EXT, 0, {}, }, {"CLRP", 0x8400, 0xffff, DSPInterpreter::clrp, nop, 1 | P_EXT, 0, {}, },
{"MOV", 0x6c00, 0xfeff, nop, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"MOV", 0x6c00, 0xfeff, DSPInterpreter::mov, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"MOVAX", 0x6800, 0xfcff, DSPInterpreter::movax, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"MOVAX", 0x6800, 0xfcff, DSPInterpreter::movax, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"MOVR", 0x6000, 0xf8ff, DSPInterpreter::movr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"MOVR", 0x6000, 0xf8ff, DSPInterpreter::movr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"MOVP", 0x6e00, 0xfeff, DSPInterpreter::movp, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"MOVP", 0x6e00, 0xfeff, DSPInterpreter::movp, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
@ -276,12 +277,6 @@ DSPOPCTemplate opcodes[] =
{"MSUBX", 0xe400, 0xfcff, DSPInterpreter::msubx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"MSUBX", 0xe400, 0xfcff, DSPInterpreter::msubx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"MADDC", 0xe800, 0xfcff, DSPInterpreter::maddc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"MADDC", 0xe800, 0xfcff, DSPInterpreter::maddc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"MSUBC", 0xec00, 0xfcff, DSPInterpreter::msubc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi}, {"MSUBC", 0xec00, 0xfcff, DSPInterpreter::msubc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
// FIXME: nakee guessing (check masks and params!)
{"TSTA?", 0xa100, 0xf7ff, DSPInterpreter::tsta, nop, 1 | P_EXT, 1, {{P_REG18, 1, 0, 11, 0x1000}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
// unknown opcode for disassemble
{"CW", 0x0000, 0x0000, nop, nop, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}}, NULL, NULL,},
}; };
DSPOPCTemplate opcodes_ext[] = DSPOPCTemplate opcodes_ext[] =