[ARM] Fix IMM support in the register cache.

This commit is contained in:
Ryan Houdek 2013-08-05 18:33:44 +00:00
parent 0d2083c670
commit 4752eae677
3 changed files with 23 additions and 6 deletions

View File

@ -59,18 +59,23 @@ void JitArm::addi(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(Integer) JITDISABLE(Integer)
u32 d = inst.RD, a = inst.RA;
ARMReg RD = gpr.R(inst.RD); if (a)
if (inst.RA)
{ {
if (gpr.IsImm(a) && gpr.IsImm(d))
{
gpr.SetImmediate(d, gpr.GetImm(d) + gpr.GetImm(a) + inst.SIMM_16);
return;
}
ARMReg rA = gpr.GetReg(false); ARMReg rA = gpr.GetReg(false);
ARMReg RA = gpr.R(inst.RA); ARMReg RA = gpr.R(inst.RA);
ARMReg RD = gpr.R(inst.RD);
MOVI2R(rA, (u32)inst.SIMM_16); MOVI2R(rA, (u32)inst.SIMM_16);
ADD(RD, RA, rA); ADD(RD, RA, rA);
} }
else else
MOVI2R(RD, inst.SIMM_16); gpr.SetImmediate(d, inst.SIMM_16);
} }
void JitArm::addis(UGeckoInstruction inst) void JitArm::addis(UGeckoInstruction inst)
{ {

View File

@ -194,6 +194,18 @@ ARMReg ArmRegCache::BindToRegister(u32 preg)
} }
} }
void ArmRegCache::SetImmediate(u32 preg, u32 imm)
{
if (regs[preg].GetType() == REG_REG)
{
// Dump real reg at this point
u32 regindex = regs[preg].GetRegIndex();
ArmCRegs[regindex].PPCReg = 33;
ArmCRegs[regindex].LastLoad = 0;
}
regs[preg].LoadToImm(imm);
}
void ArmRegCache::Flush() void ArmRegCache::Flush()
{ {
for (u8 a = 0; a < 32; ++a) for (u8 a = 0; a < 32; ++a)

View File

@ -134,7 +134,7 @@ public:
ARMReg R(u32 preg); // Returns a cached register ARMReg R(u32 preg); // Returns a cached register
bool IsImm(u32 preg) { return regs[preg].GetType() == REG_IMM; } bool IsImm(u32 preg) { return regs[preg].GetType() == REG_IMM; }
u32 GetImm(u32 preg) { return regs[preg].GetImm(); } u32 GetImm(u32 preg) { return regs[preg].GetImm(); }
void SetImmediate(u32 preg, u32 imm) { regs[preg].LoadToImm(imm); } void SetImmediate(u32 preg, u32 imm);
ARMReg BindToRegister(u32 preg); ARMReg BindToRegister(u32 preg);
}; };