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DSPLLE added carry and overflow now we (lordmark) should add them in

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the right ops ;) 


git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4222 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nakeee
2009-09-07 10:46:22 +00:00
parent 4c36a5280c
commit 49601e0af2
2 changed files with 36 additions and 5 deletions
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25
Source/Core/DSPCore/Src/DSPIntCCUtil.cpp
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@ -26,7 +26,7 @@
namespace DSPInterpreter {
void Update_SR_Register64(s64 _Value)
void Update_SR_Register64(s64 _Value, bool carry, bool overflow)
{
// TODO: Should also set 0x10 and 0x01 (also 0x02?)
g_dsp.r[DSP_REG_SR] &= ~SR_CMP_MASK;
@ -41,6 +41,16 @@ void Update_SR_Register64(s64 _Value)
g_dsp.r[DSP_REG_SR] |= SR_ARITH_ZERO;
}
if (carry)
{
g_dsp.r[DSP_REG_SR] |= SR_CARRY;
}
if (overflow)
{
g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW;
}
// Checks if top bits are equal, what is it good for?
if (((_Value >> 62) == 0) || (_Value >> 62 == 3))
{
@ -49,11 +59,10 @@ void Update_SR_Register64(s64 _Value)
}
void Update_SR_Register16(s16 _Value)
void Update_SR_Register16(s16 _Value, bool carry, bool overflow)
{
g_dsp.r[DSP_REG_SR] &= ~SR_CMP_MASK;
// Only sets those 3 bits
if (_Value < 0)
{
@ -65,6 +74,16 @@ void Update_SR_Register16(s16 _Value)
g_dsp.r[DSP_REG_SR] |= SR_ARITH_ZERO;
}
if (carry)
{
g_dsp.r[DSP_REG_SR] |= SR_CARRY;
}
if (overflow)
{
g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW;
}
// Checks if top bits are equal, what is it good for?
if (((_Value >> 14) == 0) || ((_Value >> 14) == 3))
{