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Require clang-format 9 and reformat source code

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This updates the lint script to require clang-format 9 and reformats
existing source code. Since VS2019 ships with clang-format 9 this
should make auto reformats less painful.

This also updates the clang-format configuration to set
BraceWrapping.AfterCaseLabel to true to ensure consistent brace
style; otherwise clang-format 9+ defaults to putting braces on
the same line as switch case labels.
This commit is contained in:
Léo Lam 2020-01-05 01:25:20 +01:00
parent c484276574
commit 4cc2d97294
5 changed files with 88 additions and 68 deletions
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5
Readme.md
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@ -56,11 +56,6 @@ Installer directory. This will require the Nullsoft Scriptable Install System
(NSIS) to be installed. Creating an installer is not necessary to run Dolphin (NSIS) to be installed. Creating an installer is not necessary to run Dolphin
since the Binary directory contains a working Dolphin distribution. since the Binary directory contains a working Dolphin distribution.
To ease contributing code to Dolphin which has been modified in Visual Studio,
install clang-format-7 by installing a 7.x version of the LLVM tools from http://releases.llvm.org.
In Visual Studio, under Options > Text Editor > C/C++ > Formatting > General,
enable "Use custom clang-format.exe file" and point it to the just-installed clang-format.exe
## Building for Linux and macOS ## Building for Linux and macOS
Dolphin requires [CMake](https://cmake.org/) for systems other than Windows. Many libraries are Dolphin requires [CMake](https://cmake.org/) for systems other than Windows. Many libraries are

1
Source/.clang-format
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@ -20,6 +20,7 @@ AlwaysBreakTemplateDeclarations: true
BinPackArguments: true BinPackArguments: true
BinPackParameters: true BinPackParameters: true
BraceWrapping: BraceWrapping:
AfterCaseLabel: true
AfterClass: true AfterClass: true
AfterControlStatement: true AfterControlStatement: true
AfterEnum: true AfterEnum: true

5
Source/Core/Core/IOS/USB/USBV4.cpp
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@ -77,8 +77,9 @@ void V4GetUSStringMessage::OnTransferComplete(s32 return_value) const
{ {
const std::locale& c_locale = std::locale::classic(); const std::locale& c_locale = std::locale::classic();
std::string message = Memory::GetString(data_address); std::string message = Memory::GetString(data_address);
std::replace_if(message.begin(), message.end(), std::replace_if(
[&c_locale](char c) { return !std::isprint(c, c_locale); }, '?'); message.begin(), message.end(), [&c_locale](char c) { return !std::isprint(c, c_locale); },
'?');
Memory::CopyToEmu(data_address, message.c_str(), message.size()); Memory::CopyToEmu(data_address, message.c_str(), message.size());
TransferCommand::OnTransferComplete(return_value); TransferCommand::OnTransferComplete(return_value);
} }

143
Source/Core/DolphinQt/Debugger/RegisterWidget.cpp
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@ -226,54 +226,64 @@ void RegisterWidget::PopulateTable()
for (int i = 0; i < 32; i++) for (int i = 0; i < 32; i++)
{ {
// General purpose registers (int) // General purpose registers (int)
AddRegister(i, 0, RegisterType::gpr, "r" + std::to_string(i), [i] { return GPR(i); }, AddRegister(
[i](u64 value) { GPR(i) = value; }); i, 0, RegisterType::gpr, "r" + std::to_string(i), [i] { return GPR(i); },
[i](u64 value) { GPR(i) = value; });
// Floating point registers (double) // Floating point registers (double)
AddRegister(i, 2, RegisterType::fpr, "f" + std::to_string(i), [i] { return rPS(i).PS0AsU64(); }, AddRegister(
[i](u64 value) { rPS(i).SetPS0(value); }); i, 2, RegisterType::fpr, "f" + std::to_string(i), [i] { return rPS(i).PS0AsU64(); },
[i](u64 value) { rPS(i).SetPS0(value); });
AddRegister(i, 4, RegisterType::fpr, "", [i] { return rPS(i).PS1AsU64(); }, AddRegister(
[i](u64 value) { rPS(i).SetPS1(value); }); i, 4, RegisterType::fpr, "", [i] { return rPS(i).PS1AsU64(); },
[i](u64 value) { rPS(i).SetPS1(value); });
} }
for (int i = 0; i < 8; i++) for (int i = 0; i < 8; i++)
{ {
// IBAT registers // IBAT registers
AddRegister(i, 5, RegisterType::ibat, "IBAT" + std::to_string(i), AddRegister(
[i] { i, 5, RegisterType::ibat, "IBAT" + std::to_string(i),
return (static_cast<u64>(PowerPC::ppcState.spr[SPR_IBAT0U + i * 2]) << 32) + [i] {
PowerPC::ppcState.spr[SPR_IBAT0L + i * 2]; return (static_cast<u64>(PowerPC::ppcState.spr[SPR_IBAT0U + i * 2]) << 32) +
}, PowerPC::ppcState.spr[SPR_IBAT0L + i * 2];
nullptr); },
nullptr);
// DBAT registers // DBAT registers
AddRegister(i + 8, 5, RegisterType::dbat, "DBAT" + std::to_string(i), AddRegister(
[i] { i + 8, 5, RegisterType::dbat, "DBAT" + std::to_string(i),
return (static_cast<u64>(PowerPC::ppcState.spr[SPR_DBAT0U + i * 2]) << 32) + [i] {
PowerPC::ppcState.spr[SPR_DBAT0L + i * 2]; return (static_cast<u64>(PowerPC::ppcState.spr[SPR_DBAT0U + i * 2]) << 32) +
}, PowerPC::ppcState.spr[SPR_DBAT0L + i * 2];
nullptr); },
nullptr);
// Graphics quantization registers // Graphics quantization registers
AddRegister(i + 16, 7, RegisterType::gqr, "GQR" + std::to_string(i), AddRegister(
[i] { return PowerPC::ppcState.spr[SPR_GQR0 + i]; }, nullptr); i + 16, 7, RegisterType::gqr, "GQR" + std::to_string(i),
[i] { return PowerPC::ppcState.spr[SPR_GQR0 + i]; }, nullptr);
} }
// HID registers // HID registers
AddRegister(24, 7, RegisterType::hid, "HID0", [] { return PowerPC::ppcState.spr[SPR_HID0]; }, AddRegister(
[](u64 value) { PowerPC::ppcState.spr[SPR_HID0] = static_cast<u32>(value); }); 24, 7, RegisterType::hid, "HID0", [] { return PowerPC::ppcState.spr[SPR_HID0]; },
AddRegister(25, 7, RegisterType::hid, "HID1", [] { return PowerPC::ppcState.spr[SPR_HID1]; }, [](u64 value) { PowerPC::ppcState.spr[SPR_HID0] = static_cast<u32>(value); });
[](u64 value) { PowerPC::ppcState.spr[SPR_HID1] = static_cast<u32>(value); }); AddRegister(
AddRegister(26, 7, RegisterType::hid, "HID2", [] { return PowerPC::ppcState.spr[SPR_HID2]; }, 25, 7, RegisterType::hid, "HID1", [] { return PowerPC::ppcState.spr[SPR_HID1]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_HID2] = static_cast<u32>(value); }); [](u64 value) { PowerPC::ppcState.spr[SPR_HID1] = static_cast<u32>(value); });
AddRegister(27, 7, RegisterType::hid, "HID4", [] { return PowerPC::ppcState.spr[SPR_HID4]; }, AddRegister(
[](u64 value) { PowerPC::ppcState.spr[SPR_HID4] = static_cast<u32>(value); }); 26, 7, RegisterType::hid, "HID2", [] { return PowerPC::ppcState.spr[SPR_HID2]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_HID2] = static_cast<u32>(value); });
AddRegister(
27, 7, RegisterType::hid, "HID4", [] { return PowerPC::ppcState.spr[SPR_HID4]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_HID4] = static_cast<u32>(value); });
for (int i = 0; i < 16; i++) for (int i = 0; i < 16; i++)
{ {
// SR registers // SR registers
AddRegister(i, 7, RegisterType::sr, "SR" + std::to_string(i), AddRegister(
[i] { return PowerPC::ppcState.sr[i]; }, i, 7, RegisterType::sr, "SR" + std::to_string(i), [i] { return PowerPC::ppcState.sr[i]; },
[i](u64 value) { PowerPC::ppcState.sr[i] = value; }); [i](u64 value) { PowerPC::ppcState.sr[i] = value; });
} }
// Special registers // Special registers
@ -281,58 +291,71 @@ void RegisterWidget::PopulateTable()
AddRegister(16, 5, RegisterType::tb, "TB", PowerPC::ReadFullTimeBaseValue, nullptr); AddRegister(16, 5, RegisterType::tb, "TB", PowerPC::ReadFullTimeBaseValue, nullptr);
// PC // PC
AddRegister(17, 5, RegisterType::pc, "PC", [] { return PowerPC::ppcState.pc; }, AddRegister(
[](u64 value) { PowerPC::ppcState.pc = value; }); 17, 5, RegisterType::pc, "PC", [] { return PowerPC::ppcState.pc; },
[](u64 value) { PowerPC::ppcState.pc = value; });
// LR // LR
AddRegister(18, 5, RegisterType::lr, "LR", [] { return PowerPC::ppcState.spr[SPR_LR]; }, AddRegister(
[](u64 value) { PowerPC::ppcState.spr[SPR_LR] = value; }); 18, 5, RegisterType::lr, "LR", [] { return PowerPC::ppcState.spr[SPR_LR]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_LR] = value; });
// CTR // CTR
AddRegister(19, 5, RegisterType::ctr, "CTR", [] { return PowerPC::ppcState.spr[SPR_CTR]; }, AddRegister(
[](u64 value) { PowerPC::ppcState.spr[SPR_CTR] = value; }); 19, 5, RegisterType::ctr, "CTR", [] { return PowerPC::ppcState.spr[SPR_CTR]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_CTR] = value; });
// CR // CR
AddRegister(20, 5, RegisterType::cr, "CR", [] { return PowerPC::ppcState.cr.Get(); }, AddRegister(
[](u64 value) { PowerPC::ppcState.cr.Set(value); }); 20, 5, RegisterType::cr, "CR", [] { return PowerPC::ppcState.cr.Get(); },
[](u64 value) { PowerPC::ppcState.cr.Set(value); });
// XER // XER
AddRegister(21, 5, RegisterType::xer, "XER", [] { return PowerPC::GetXER().Hex; }, AddRegister(
[](u64 value) { PowerPC::SetXER(UReg_XER(value)); }); 21, 5, RegisterType::xer, "XER", [] { return PowerPC::GetXER().Hex; },
[](u64 value) { PowerPC::SetXER(UReg_XER(value)); });
// FPSCR // FPSCR
AddRegister(22, 5, RegisterType::fpscr, "FPSCR", [] { return PowerPC::ppcState.fpscr.Hex; }, AddRegister(
[](u64 value) { PowerPC::ppcState.fpscr = static_cast<u32>(value); }); 22, 5, RegisterType::fpscr, "FPSCR", [] { return PowerPC::ppcState.fpscr.Hex; },
[](u64 value) { PowerPC::ppcState.fpscr = static_cast<u32>(value); });
// MSR // MSR
AddRegister(23, 5, RegisterType::msr, "MSR", [] { return PowerPC::ppcState.msr.Hex; }, AddRegister(
[](u64 value) { PowerPC::ppcState.msr.Hex = value; }); 23, 5, RegisterType::msr, "MSR", [] { return PowerPC::ppcState.msr.Hex; },
[](u64 value) { PowerPC::ppcState.msr.Hex = value; });
// SRR 0-1 // SRR 0-1
AddRegister(24, 5, RegisterType::srr, "SRR0", [] { return PowerPC::ppcState.spr[SPR_SRR0]; }, AddRegister(
[](u64 value) { PowerPC::ppcState.spr[SPR_SRR0] = value; }); 24, 5, RegisterType::srr, "SRR0", [] { return PowerPC::ppcState.spr[SPR_SRR0]; },
AddRegister(25, 5, RegisterType::srr, "SRR1", [] { return PowerPC::ppcState.spr[SPR_SRR1]; }, [](u64 value) { PowerPC::ppcState.spr[SPR_SRR0] = value; });
[](u64 value) { PowerPC::ppcState.spr[SPR_SRR1] = value; }); AddRegister(
25, 5, RegisterType::srr, "SRR1", [] { return PowerPC::ppcState.spr[SPR_SRR1]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_SRR1] = value; });
// Exceptions // Exceptions
AddRegister(26, 5, RegisterType::exceptions, "Exceptions", AddRegister(
[] { return PowerPC::ppcState.Exceptions; }, 26, 5, RegisterType::exceptions, "Exceptions", [] { return PowerPC::ppcState.Exceptions; },
[](u64 value) { PowerPC::ppcState.Exceptions = value; }); [](u64 value) { PowerPC::ppcState.Exceptions = value; });
// Int Mask // Int Mask
AddRegister(27, 5, RegisterType::int_mask, "Int Mask", AddRegister(
[] { return ProcessorInterface::GetMask(); }, nullptr); 27, 5, RegisterType::int_mask, "Int Mask", [] { return ProcessorInterface::GetMask(); },
nullptr);
// Int Cause // Int Cause
AddRegister(28, 5, RegisterType::int_cause, "Int Cause", AddRegister(
[] { return ProcessorInterface::GetCause(); }, nullptr); 28, 5, RegisterType::int_cause, "Int Cause", [] { return ProcessorInterface::GetCause(); },
nullptr);
// DSISR // DSISR
AddRegister(29, 5, RegisterType::dsisr, "DSISR", [] { return PowerPC::ppcState.spr[SPR_DSISR]; }, AddRegister(
[](u64 value) { PowerPC::ppcState.spr[SPR_DSISR] = value; }); 29, 5, RegisterType::dsisr, "DSISR", [] { return PowerPC::ppcState.spr[SPR_DSISR]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_DSISR] = value; });
// DAR // DAR
AddRegister(30, 5, RegisterType::dar, "DAR", [] { return PowerPC::ppcState.spr[SPR_DAR]; }, AddRegister(
[](u64 value) { PowerPC::ppcState.spr[SPR_DAR] = value; }); 30, 5, RegisterType::dar, "DAR", [] { return PowerPC::ppcState.spr[SPR_DAR]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_DAR] = value; });
// Hash Mask // Hash Mask
AddRegister( AddRegister(

2
Tools/lint.sh
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@ -9,7 +9,7 @@ if ! [ -x "$(command -v git)" ]; then
exit 1 exit 1
fi fi
REQUIRED_CLANG_FORMAT_MAJOR=7 REQUIRED_CLANG_FORMAT_MAJOR=9
REQUIRED_CLANG_FORMAT_MINOR=0 REQUIRED_CLANG_FORMAT_MINOR=0
CLANG_FORMAT=clang-format CLANG_FORMAT=clang-format
CLANG_FORMAT_MAJOR=clang-format-${REQUIRED_CLANG_FORMAT_MAJOR} CLANG_FORMAT_MAJOR=clang-format-${REQUIRED_CLANG_FORMAT_MAJOR}