From 307a1e3ab869d30987593d5879fa71f6b565f431 Mon Sep 17 00:00:00 2001 From: mitaclaw <140017135+mitaclaw@users.noreply.github.com> Date: Fri, 26 Apr 2024 10:58:16 -0700 Subject: [PATCH 1/2] Jit64/JitArm64: Check Breakpoints Before FPU Availability CachedInterpreter already does it in the expected order. --- Source/Core/Core/PowerPC/Jit64/Jit.cpp | 48 +++++++++---------- Source/Core/Core/PowerPC/JitArm64/Jit.cpp | 58 +++++++++++------------ 2 files changed, 53 insertions(+), 53 deletions(-) diff --git a/Source/Core/Core/PowerPC/Jit64/Jit.cpp b/Source/Core/Core/PowerPC/Jit64/Jit.cpp index 79d920a1d1..7aa0263fcd 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit.cpp @@ -1035,6 +1035,30 @@ bool Jit64::DoJit(u32 em_address, JitBlock* b, u32 nextPC) } else { + auto& cpu = m_system.GetCPU(); + auto& power_pc = m_system.GetPowerPC(); + if (m_enable_debugging && power_pc.GetBreakPoints().IsAddressBreakPoint(op.address) && + !cpu.IsStepping()) + { + gpr.Flush(); + fpr.Flush(); + + MOV(32, PPCSTATE(pc), Imm32(op.address)); + ABI_PushRegistersAndAdjustStack({}, 0); + ABI_CallFunctionP(PowerPC::CheckBreakPointsFromJIT, &power_pc); + ABI_PopRegistersAndAdjustStack({}, 0); + MOV(64, R(RSCRATCH), ImmPtr(cpu.GetStatePtr())); + TEST(32, MatR(RSCRATCH), Imm32(0xFFFFFFFF)); + FixupBranch noBreakpoint = J_CC(CC_Z); + + Cleanup(); + MOV(32, PPCSTATE(npc), Imm32(op.address)); + SUB(32, PPCSTATE(downcount), Imm32(js.downcountAmount)); + JMP(asm_routines.dispatcher_exit, Jump::Near); + + SetJumpTarget(noBreakpoint); + } + if ((opinfo->flags & FL_USE_FPU) && !js.firstFPInstructionFound) { // This instruction uses FPU - needs to add FP exception bailout @@ -1061,30 +1085,6 @@ bool Jit64::DoJit(u32 em_address, JitBlock* b, u32 nextPC) js.firstFPInstructionFound = true; } - auto& cpu = m_system.GetCPU(); - auto& power_pc = m_system.GetPowerPC(); - if (m_enable_debugging && power_pc.GetBreakPoints().IsAddressBreakPoint(op.address) && - !cpu.IsStepping()) - { - gpr.Flush(); - fpr.Flush(); - - MOV(32, PPCSTATE(pc), Imm32(op.address)); - ABI_PushRegistersAndAdjustStack({}, 0); - ABI_CallFunctionP(PowerPC::CheckBreakPointsFromJIT, &power_pc); - ABI_PopRegistersAndAdjustStack({}, 0); - MOV(64, R(RSCRATCH), ImmPtr(cpu.GetStatePtr())); - TEST(32, MatR(RSCRATCH), Imm32(0xFFFFFFFF)); - FixupBranch noBreakpoint = J_CC(CC_Z); - - Cleanup(); - MOV(32, PPCSTATE(npc), Imm32(op.address)); - SUB(32, PPCSTATE(downcount), Imm32(js.downcountAmount)); - JMP(asm_routines.dispatcher_exit, Jump::Near); - - SetJumpTarget(noBreakpoint); - } - if (bJITRegisterCacheOff) { gpr.Flush(); diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp index 1064da5517..22476210ae 100644 --- a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp @@ -1169,35 +1169,6 @@ bool JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC) } else { - if ((opinfo->flags & FL_USE_FPU) && !js.firstFPInstructionFound) - { - // This instruction uses FPU - needs to add FP exception bailout - ARM64Reg WA = gpr.GetReg(); - LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(msr)); - FixupBranch b1 = TBNZ(WA, 13); // Test FP enabled bit - - FixupBranch far_addr = B(); - SwitchToFarCode(); - SetJumpTarget(far_addr); - - gpr.Flush(FlushMode::MaintainState, WA); - fpr.Flush(FlushMode::MaintainState, ARM64Reg::INVALID_REG); - - LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions)); - ORR(WA, WA, LogicalImm(EXCEPTION_FPU_UNAVAILABLE, GPRSize::B32)); - STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions)); - - gpr.Unlock(WA); - - WriteExceptionExit(js.compilerPC, false, true); - - SwitchToNearCode(); - - SetJumpTarget(b1); - - js.firstFPInstructionFound = true; - } - if (m_enable_debugging && !cpu.IsStepping() && m_system.GetPowerPC().GetBreakPoints().IsAddressBreakPoint(op.address)) { @@ -1228,6 +1199,35 @@ bool JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC) SetJumpTarget(no_breakpoint); } + if ((opinfo->flags & FL_USE_FPU) && !js.firstFPInstructionFound) + { + // This instruction uses FPU - needs to add FP exception bailout + ARM64Reg WA = gpr.GetReg(); + LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(msr)); + FixupBranch b1 = TBNZ(WA, 13); // Test FP enabled bit + + FixupBranch far_addr = B(); + SwitchToFarCode(); + SetJumpTarget(far_addr); + + gpr.Flush(FlushMode::MaintainState, WA); + fpr.Flush(FlushMode::MaintainState, ARM64Reg::INVALID_REG); + + LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions)); + ORR(WA, WA, LogicalImm(EXCEPTION_FPU_UNAVAILABLE, GPRSize::B32)); + STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions)); + + gpr.Unlock(WA); + + WriteExceptionExit(js.compilerPC, false, true); + + SwitchToNearCode(); + + SetJumpTarget(b1); + + js.firstFPInstructionFound = true; + } + if (bJITRegisterCacheOff) { FlushCarry(); From 756ea81ab24753c4cd217ac969170e01f149af93 Mon Sep 17 00:00:00 2001 From: mitaclaw <140017135+mitaclaw@users.noreply.github.com> Date: Sun, 28 Apr 2024 15:54:15 -0700 Subject: [PATCH 2/2] Jit64: Smaller Instruction Breakpoint Condition Also some static_asserts in JitArm64. --- Source/Core/Core/PowerPC/Jit64/Jit.cpp | 5 +++-- Source/Core/Core/PowerPC/Jit64/JitAsm.cpp | 9 +++++---- Source/Core/Core/PowerPC/JitArm64/Jit.cpp | 2 ++ Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp | 3 +++ 4 files changed, 13 insertions(+), 6 deletions(-) diff --git a/Source/Core/Core/PowerPC/Jit64/Jit.cpp b/Source/Core/Core/PowerPC/Jit64/Jit.cpp index 7aa0263fcd..ce63b2e3c4 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit.cpp @@ -16,6 +16,7 @@ #endif #include "Common/CommonTypes.h" +#include "Common/EnumUtils.h" #include "Common/GekkoDisassembler.h" #include "Common/IOFile.h" #include "Common/Logging/Log.h" @@ -1048,8 +1049,8 @@ bool Jit64::DoJit(u32 em_address, JitBlock* b, u32 nextPC) ABI_CallFunctionP(PowerPC::CheckBreakPointsFromJIT, &power_pc); ABI_PopRegistersAndAdjustStack({}, 0); MOV(64, R(RSCRATCH), ImmPtr(cpu.GetStatePtr())); - TEST(32, MatR(RSCRATCH), Imm32(0xFFFFFFFF)); - FixupBranch noBreakpoint = J_CC(CC_Z); + CMP(32, MatR(RSCRATCH), Imm32(Common::ToUnderlying(CPU::State::Running))); + FixupBranch noBreakpoint = J_CC(CC_E); Cleanup(); MOV(32, PPCSTATE(npc), Imm32(op.address)); diff --git a/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp b/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp index 7b0e3e8242..e5afb50e07 100644 --- a/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp +++ b/Source/Core/Core/PowerPC/Jit64/JitAsm.cpp @@ -6,6 +6,7 @@ #include #include "Common/CommonTypes.h" +#include "Common/EnumUtils.h" #include "Common/JitRegister.h" #include "Common/x64ABI.h" #include "Common/x64Emitter.h" @@ -105,8 +106,8 @@ void Jit64AsmRoutineManager::Generate() if (enable_debugging) { MOV(64, R(RSCRATCH), ImmPtr(system.GetCPU().GetStatePtr())); - TEST(32, MatR(RSCRATCH), Imm32(0xFFFFFFFF)); - dbg_exit = J_CC(CC_NZ, Jump::Near); + CMP(32, MatR(RSCRATCH), Imm32(Common::ToUnderlying(CPU::State::Running))); + dbg_exit = J_CC(CC_NE, Jump::Near); } SetJumpTarget(skipToRealDispatch); @@ -236,8 +237,8 @@ void Jit64AsmRoutineManager::Generate() // Check the state pointer to see if we are exiting // Gets checked on at the end of every slice MOV(64, R(RSCRATCH), ImmPtr(system.GetCPU().GetStatePtr())); - TEST(32, MatR(RSCRATCH), Imm32(0xFFFFFFFF)); - J_CC(CC_Z, outerLoop); + CMP(32, MatR(RSCRATCH), Imm32(Common::ToUnderlying(CPU::State::Running))); + J_CC(CC_E, outerLoop); // Landing pad for drec space dispatcher_exit = GetCodePtr(); diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp index 22476210ae..9372850448 100644 --- a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp @@ -7,6 +7,7 @@ #include "Common/Arm64Emitter.h" #include "Common/CommonTypes.h" +#include "Common/EnumUtils.h" #include "Common/Logging/Log.h" #include "Common/MathUtil.h" #include "Common/MsgHandler.h" @@ -1185,6 +1186,7 @@ bool JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC) LDR(IndexType::Unsigned, ARM64Reg::W0, ARM64Reg::X0, MOVPage2R(ARM64Reg::X0, cpu.GetStatePtr())); + static_assert(Common::ToUnderlying(CPU::State::Running) == 0); FixupBranch no_breakpoint = CBZ(ARM64Reg::W0); Cleanup(); diff --git a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp index cd93fccebf..380b935d64 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp @@ -9,6 +9,7 @@ #include "Common/BitUtils.h" #include "Common/CommonTypes.h" #include "Common/Config/Config.h" +#include "Common/EnumUtils.h" #include "Common/FloatUtils.h" #include "Common/JitRegister.h" #include "Common/MathUtil.h" @@ -88,6 +89,7 @@ void JitArm64::GenerateAsm() { LDR(IndexType::Unsigned, ARM64Reg::W8, ARM64Reg::X8, MOVPage2R(ARM64Reg::X8, cpu.GetStatePtr())); + static_assert(Common::ToUnderlying(CPU::State::Running) == 0); debug_exit = CBNZ(ARM64Reg::W8); } @@ -195,6 +197,7 @@ void JitArm64::GenerateAsm() // Check the state pointer to see if we are exiting // Gets checked on at the end of every slice LDR(IndexType::Unsigned, ARM64Reg::W8, ARM64Reg::X8, MOVPage2R(ARM64Reg::X8, cpu.GetStatePtr())); + static_assert(Common::ToUnderlying(CPU::State::Running) == 0); FixupBranch exit = CBNZ(ARM64Reg::W8); SetJumpTarget(to_start_of_timing_slice);